Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022
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3.2.1. Clock Interface

Platform Designer generates the clock source BFM for the FPGA-to-HPS alternate clock source.

Table 15.  HPS Clock Input Interface Simulation ModelThe Intel® clock source BFM application programming interface (API) applies to the BFM listed in this table. Your Verilog interfaces use the same API.

Interface Name

BFM Instance Name

f2h_free_clk f2h_free_clock_inst

Platform Designer generates the clock source BFM for each clock output interface from the HPS component. For HPS-to-FPGA user clocks, specify the BFM clock rate in the User clock frequency field in the HPS Clocks page when instantiating the HPS component in Platform Designer.

The HPS-to-FPGA debug APB interface generates a clock output to the FPGA, named h2f_debug_apb_clock. In simulation, the clock source BFM also represents this clock output’s behavior.

Table 16.  HPS Clock Output Interface Simulation ModelThe Intel® clock source BFM application programming interface (API) applies to all the BFMs listed in this table. Your Verilog interfaces use the same API.

Interface Name

BFM Instance Name

h2f_user0_clock h2f_user0_clock_inst
h2f_user1_clock h2f_user1_clock_inst