3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
22.214.171.124. HPS Peripheral Clocks – Desired Frequencies
The clock frequencies you provide in this section are reported in a Synopsys* Design Constraints File (.sdc) generated by Platform Designer. The .sdc file is referenced in the system .qip file when the system is generated.
- The L3 clock frequency allows you to configure the frequency of the L3 interconnect. For more information about the maximum frequency of this clock, refer to the Intel Stratix 10 Device Datasheet.
- The L4 free clock frequency dropdown displays the frequency of the free-running L4 clock.
- The L4 main clock frequency dropdown allows you to select the desired frequency of the L4 interconnect clock, which is input to the fast peripherals including DMA, SPIM, SPIS, and TCM.
- The L4 peripheral slow clock frequency dropdown allows you to select the desired frequency of the L4 interconnect input to the slow peripherals, including Timer, I2C, and UART.
- The CoreSight clock frequency dropdown allows you to select the desired clock frequency for the CoreSight trace and debug time stamp clock.
- The CoreSight bus clock frequency dropdown displays the default CoreSight bus clock frequency.
- The CoreSight trace IO clock dropdown allows you to select the frequency for the CoreSight trace I/Os. This is an independent clock and is configurable down to 50MHz for lower speed debuggers.
- The Frequency for GPIO debouncer field allows you to specify an input clock frequency to the GPIO controller to be used by the optional debounce circuitry. The external signal can be debounced to remove any spurious glitches that are less than one period of the debouncing clock. When input signals are debounced using this clock, the signals must be active for a minimum of two cycles to guarantee that they are registered.
- The EMAC<n> clock frequency dropdowns are enabled when the corresponding EMAC peripherals are enabled. These dropdowns allow you to select the reference clock for each EMAC, which must be either 50MHz or 250MHz
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