Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.3.2.4. Clock Sources

The drop-downs in this section control multiplexers in the HPS clock manager to select the source for the corresponding PLL or clock. Some of the drop-downs are enabled only when the corresponding peripherals are enabled. The FPGA to HPS Free clock is available as an option in these drop-downs when it is enabled on the Input Clocks tab.
Note: If you intend to use the FPGA to HPS free clock as the input to the hps_osc_clk pin, you must select that option for the Main PLL reference clock source and Peripheral PLL reference clock source.

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