Intel® Stratix® 10 Hard Processor System Component Reference Manual

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ID 683516
Date 12/14/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component 2. Configuring the Intel® Stratix® 10 Hard Processor System Component 3. Simulating the Intel® Stratix® 10 HPS Component
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component x
1.1. Cortex*-A53 MPCore* Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Intel® Stratix® 10 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. SDRAM 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR ARM Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface 2.2.2.4. FPGA-to-HPS SDRAM AXI* -4 Slave Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.6. Pin MUX and Peripherals x
2.6.1. Auto-Place IP 2.6.2. Advanced
3. Simulating the Intel® Stratix® 10 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. Running the Simulations
3.1.1. Setting Up the HPS Component for Simulation x
3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
3.1.3. Running the Simulations x
3.1.3.1. Running HPS RTL Simulation 3.1.3.2. Running HPS Post-Fit Simulation
3.1.3.2. Running HPS Post-Fit Simulation x
3.1.3.2.1. Post-Fit Simulation Files 3.1.3.2.2. BFM API Hierarchy Format
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component
2. Configuring the Intel® Stratix® 10 Hard Processor System Component
3. Simulating the Intel® Stratix® 10 HPS Component

3.12. FPGA-to-HPS DMA Handshake Interface

The FPGA‑to‑HPS DMA handshake interface is connected to an Intel® conduit BFM for simulation. The following table lists the name for each interface, along with API function names for each type of simulation. You can monitor the interface state changes or set the interface by using the API listed.

Table 30.  FPGA-to-HPS DMA Handshake Interface Simulation ModelThe usage of conduit get_*() and set_*() API functions is the same as with the general Avalon® conduit BFM.

Interface Name

BFM Instance Name

RTL Simulation API Function Names

Post‑Fit Simulation API Function Names

f2h_dma0 f2h_dma0_inst

get_f2h_dma0_req()

get_f2h_dma0_single()

set_f2h_dma0_ack() 

get_channel0_req()
get_channel0_single()
set_channel0_xx_ack()
f2h_dma1 f2h_dma1_inst

get_f2h_dma1_req()

get_f2h_dma1_single()

set_f2h_dma1_ack() 

get_channel1_req()
get_channel1_single()
set_channel1_xx_ack()
f2h_dma2 f2h_dma2_inst

get_f2h_dma2_req()

get_f2h_dma2_single()

set_f2h_dma2_ack() 

get_channel2_req()
get_channel2_single()
set_channel2_xx_ack()
f2h_dma3 f2h_dma3_inst

get_f2h_dma3_req()

get_f2h_dma3_single()

set_f2h_dma3_ack() 

get_channel3_req()
get_channel3_single()
set_channel3_xx_ack()
f2h_dma4 f2h_dma4_inst

get_f2h_dma4_req()

get_f2h_dma4_single()

set_f2h_dma4_ack() 

get_channel4_req()
get_channel4_single()
set_channel4_xx_ack()
f2h_dma5 f2h_dma5_inst

get_f2h_dma5_req()

get_f2h_dma5_single()

set_f2h_dma5_ack() 

get_channel5_req()
get_channel5_single()
set_channel5_xx_ack()
f2h_dma6 f2h_dma6_inst

get_f2h_dma6_req()

get_f2h_dma6_single()

set_f2h_dma6_ack() 

get_channel6_req()
get_channel6_single()
set_channel6_xx_ack()
f2h_dma7 f2h_dma7_inst

get_f2h_dma7_req()

get_f2h_dma7_single()

set_f2h_dma7_ack() 

get_channel7_req()
get_channel7_single()
set_channel7_xx_ack()
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