Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022

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3.1.2. Generating the HPS Simulation Model in Platform Designer

The following steps outline how to generate the simulation model:

  1. In Platform Designer, click Generate HDL under the Generate menu.
  2. Choose between RTL and post–fit simulation
    For RTL simulation, perform the following steps:
    1. Set Create simulation model to Verilog.
    2. Click Generate.1
    For post–fit simulation, perform the following steps:
    1. Turn on the Create HDL design files for synthesis option.
    2. Turn on the Create block symbol file (.bsf) option.2 3
  3. Click Generate.
1 VHDL is supported for HPS simulation and requires a mix language simulator. However, the BFMs always need to be in verilog. Custom components can be in VHDL.
2 A .bsf file is only needed for schematic entry.
3 This is not a requirement for simulation or implementation unless a schematic is used.