3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
3.1.2. Generating the HPS Simulation Model in Platform Designer
The following steps outline how to generate the simulation model:
- In Platform Designer, click Generate HDL under the Generate menu.
- Choose between RTL and post–fit simulation
For RTL simulation, perform the following steps:
For post–fit simulation, perform the following steps:
- Set Create simulation model to Verilog.
- Click Generate.1
- Click Generate.
1 VHDL is supported for HPS simulation and requires a mix language simulator. However, the BFMs always need to be in verilog. Custom components can be in VHDL.
2 A .bsf file is only needed for schematic entry.
3 This is not a requirement for simulation or implementation unless a schematic is used.
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