Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

3.1.3.2.1. Post-Fit Simulation Files

Post-fit simulation is the simulation of the netlist generated from the original RTL design after it has been mapped, synthesized, and fit. The netlist represents the actual hardware and its connections as they appear in the FPGA. Intel® Quartus® Prime generates the netlist and can generate a Standard Delay Format (.sdf) file with the timing information for all connections. The simulation can be functional only (without the timing information) where all wires and gates take zero time, or it can be a timing simulation where the time for all transitions is based on the SDF information.

Post-fit simulation can serve a number of different purposes:
  • Used to perform a dynamic verification of the timing of the design.
  • Used to verify the functional correctness of either the design, the compilation flow (in particular, the fitter), or both.

This table uses the following symbols:

  • <ACDS install> = Intel® Complete Design Suite installation path
  • <Avalon Verification IP> = <ACDS install> /ip/altera/sopc_builder_ip/verification
  • <AXI Verification IP> = <ACDS install> /ip/altera/mentor_vip_ae
  • <HPS Post‑fit Sim> = <ACDS install> /ip/altera/hps/postfitter_simulation
  • <Device Sim Lib> = <ACDS install> /quartus/eda/sim_lib
Table 14.  Post-Fit Simulation Files

Library

Directory

File

Intel® Verification IP Library

<Avalon Verification IP>/lib/

verbosity_pkg.sv

avalon_mm_pkg.sv

avalon_utilities_pkg.sv

Avalon Clock Source BFM

<Avalon Verification IP>/altera_avalon_clock_source/

altera_avalon_clock_source.sv

Avalon Reset Source BFM

<Avalon Verification IP>/altera_avalon_reset_source/

altera_avalon_reset_source.sv

Avalon MM Slave BFM

<Avalon Verification IP>/altera_avalon_mm_slave_bfm/

altera_avalon_mm_slave_bfm.sv

Avalon Interrupt Sink BFM

<Avalon Verification IP>/altera_avalon_interrupt_sink/

altera_avalon_interrupt_sink.sv

Mentor AXI Verification IP Library

<AXI Verification IP>/common/

questa_mvc_svapi.svh

Mentor AXI3 BFM

<AXI Verification IP>/axi3/axi3/bfm/

mgc_common_axi.sv

mgc_axi_master.sv

mgc_axi_slave.sv

HPS Post‑Fit Simulation Library

<HPS Post‑fit Sim>/

All the files in the directory

Device Simulation Library4

<Device Sim Lib>/

altera_primitives.v

220model.v

sgate.v

altera_mf.v

altera_lnsim.sv

twentynm_atoms.v

fourteennm_atoms.sv

mentor/twentynm_atoms_ncrypt.sv

mentor/fourteennm_atoms_ncrypt.sv

EDA Netlist Writer Generated Post‑Fit Simulation Model

<User project directory>/

*.vo

*.vho

(Mixed‑language simulator is needed for Verilog HDL and VHDL mixed design)

User testbench files

<User project directory>/

*.v

*.sv

*.vhd

(Mixed‑language simulator is needed for Verilog HDL and VHDL mixed design)

4 The device simulation library is not needed with Modelsim‑ Intel® .

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