Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

3.1. Simulation Flows

Intel® provides a functional register transfer level (RTL) simulation and a post–fitter gate–level simulation flow. Both simulation flows involve the following major steps, which is defined in the following sections:

  1. Setting up the HPS component for simulation.
  2. Generating the HPS simulation model in Platform Designer.
  3. Running the simulation.

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