Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.2.5.1. FPGA-to-HPS

Turning on the Enable FPGA-to-HPS Interrupts option configures the HPS component to provide 64 general purpose FPGA-to-HPS interrupts, allowing soft IP in the FPGA fabric to trigger interrupts to the MPU’s generic interrupt controller (GIC). The interrupts are implemented through the following 32-bit interfaces:
  • f2h_irq0—FPGA-to-HPS interrupts 0 through 31
  • f2h_irq1—FPGA-to-HPS interrupts 32 through 63

The FPGA-to-HPS interrupts are asynchronous on the FPGA interface. Inside the HPS, the interrupts are synchronized to the MPU’s internal peripheral clock (mpu_periph_clk).

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