The interconnect consists of the L3 interconnect, SDRAM L3 interconnect, and level 4 (L4) buses.
The L3 Interconnect provides high-bandwidth routing featuring Arm* TrustZone* -compliant security firewalls with programmable Quality of Service (QoS) between masters and slaves in the HPS. The L3 Interconnect also provides a lower performance tier of L4 buses for mid to low-bandwidth slave peripherals and peripheral control and status registers. The SDRAM L3 interconnect connects the HPS to the hard memory controller located in the FPGA I/O column.
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