Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.2.1.3. Enable Debug APB Interface

The debug Advanced Peripheral Bus (APB)* interface allows debug components in the FPGA fabric to access debug components in the HPS.

For more information about the Debug APB interface, refer to the “CoreSight Debug and Trace” chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.

Turning on this option enables the following interfaces and signals:
Table 2.  APB Interfaces and Signals
Interface Name Interface Type Signals
h2f_debug_apb_clock Clock Input h2f_dbg_apb_clk
h2f_debug_apb_reset Reset Output h2f_dbg_apb_rst_n
h2f_debug_apb APB Master h2f_dbg_apb_PADDR[14..0] h2f_dbg_apb_PADDR31 h2f_dbg_apb_PENABLE h2f_dbg_apb_PRDATA[31..0] h2f_dbg_apb_PREADY h2f_dbg_apb_PSEL h2f_dbg_apb_PSLVERB h2f_dbg_apb_PWDATA[31..0] h2f_dbg_apb_PWRITE
h2f_debug_apb_sideband Conduit h2f_debug_apb_PCLKEN h2f_debug_apb_DBG_APB_DISABLE

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