Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.2.2.3. Lightweight HPS to FPGA Master Interface

The lightweight HPS-to-FPGA interface, a low-bandwidth control interface, allows HPS masters to issue transactions to the FPGA fabric. The Enable/Data Width dropdown is thus limited to a fixed 32-bit data width. The Ready Latency pipeline drop-down configures the flexible ready latency pipelining available in the FPGA fabric. This can assist with timing closure at the FPGA-to-HPS boundary and is configurable to depths of 0 (none), 1, 2, 3, or 4. The Bridge address width is configurable to either 21 bits or 20 bits. When this bridge is enabled, the interfaces h2f_lw_axi_master, h2f_lw_axi_clock, and h2f_lw_axi_reset are made available.

This bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally. The exposed AXI* interface operates on the same clock domain as the clock supplied by the FPGA fabric. Other interface standards in the FPGA fabric, such as connecting to Avalon® -MM interfaces, can be supported through the use of soft logic adapters. The Platform Designer system integration tool automatically generates adapter logic to connect AXI* to Avalon® -MM interfaces.

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