Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.2.1.5. Enable FPGA Cross Trigger Interface

The cross trigger interface (CTI) allows trigger sources and sinks in FPGA logic to interface with the embedded cross trigger (ECT).

For more information about the FPGA Cross Trigger interface, refer to the “CoreSight Debug and Trace” chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.

If this interface must be connected to a Signal Tap II instance in the FPGA fabric, then it must be left disabled in Platform Designer. Turning on the Enable FPGA Cross Trigger Interface option enables the h2f_cti conduit, which is comprised of the following signals:
  • h2f_cti_trig_in [7..0]
  • h2f_cti_trig_out_ack [7..0]
  • h2f_cti_trig_out [7..0]
  • h2f_cti_trig_in_ack [7..0]

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