Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.7. Generating and Compiling the HPS Component

The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer project. Perform the following steps:

  1. Generate the design with Platform Designer. The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
  2. Add <qsys_system_name>.qip to the Intel® Quartus® Prime project. <qsys_system_name>.qip is the Intel® Quartus® Prime IP File for the HPS component, generated by Platform Designer.
    Note: Platform Designer generates pin assignments in the .qip file.
  3. Perform analysis and synthesis with the Intel® Quartus® Prime software.
  4. Compile the design with the Intel® Quartus® Prime software.
  5. Optionally back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.

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