Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.3.1.2. FPGA-to-HPS Clocks Source

Turning on the Enable FPGA-to-HPS free clock option enables the f2h_free_clk clock input. This is an alternative input to the main HPS PLL driven from the FPGA fabric instead of the dedicated hps_osc_clk pin. Turning on the Enable FPGA-to-HPS free clock option is subject to the same requirements as that pin.

For more information about the requirements for this clock, refer to the Intel Stratix 10 Device Datasheet.

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