Intel® Arria® 10 SoC Development Kit User Guide

ID 683227
Date 7/12/2023
Document Table of Contents

5.9.6. USB 2.0 Port (HPS)

The development supports one USB2.0 interface. The HPS USB interface is connected to a USB3320 PHY that is connected to a micro-USB connector (J4).

Table 38.  USB 2.0 FPGA Signal Names and Functions
FPGA Pin Assignment Shared I/O Bit Schematic Signal Name Description
D18 GPIO0_IO0 USB_CLK USB2.0 Clock
E18 GPIO0_IO1 USB_STP USB2.0 Stop bit
C19 GPIO0_IO2 USB_DIR USB2.0 direction bit
D19 GPIO0_IO3 USB_DATA0 USB2.0 data line 0
E17 GPIO0_IO4 USB_DATA1 USB2.0 data line 1
C17 GPIO0_IO6 USB_DATA2 USB2.0 data line 2
C18 GPIO0_IO7 USB_DATA3 USB2.0 data line 3
D21 GPIO0_IO8 USB_DATA4 USB2.0 data line 4
D20 GPIO0_IO9 USB_DATA5 USB2.0 data line 5
E21 GPIO0_IO10 USB_DATA6 USB2.0 data line 6
E22 GPIO0_IO11 USB_DATA7 USB2.0 data line 7

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