Visible to Intel only — GUID: iga1438035891606
Ixiasoft
5.9.1. PCI Express
5.9.2. 10/100/1000 Ethernet (HPS)
5.9.3. 10/100/1000 Ethernet (FPGA)
5.9.4. FMC
5.9.5. HPS Shared I/O
5.9.6. USB 2.0 Port (HPS)
5.9.7. RS-232 UART (HPS)
5.9.8. Real-Time Clock (HPS)
5.9.9. SFP+
5.9.10. I2C Interface
5.9.11. FPGA General I/O Configuration
5.9.12. HPS SPIO Interface
Visible to Intel only — GUID: iga1438035891606
Ixiasoft
5.9.6. USB 2.0 Port (HPS)
The development supports one USB2.0 interface. The HPS USB interface is connected to a USB3320 PHY that is connected to a micro-USB connector (J4).
FPGA Pin Assignment | Shared I/O Bit | Schematic Signal Name | Description |
---|---|---|---|
D18 | GPIO0_IO0 | USB_CLK | USB2.0 Clock |
E18 | GPIO0_IO1 | USB_STP | USB2.0 Stop bit |
C19 | GPIO0_IO2 | USB_DIR | USB2.0 direction bit |
D19 | GPIO0_IO3 | USB_DATA0 | USB2.0 data line 0 |
E17 | GPIO0_IO4 | USB_DATA1 | USB2.0 data line 1 |
F17 | GPIO0_IO5 | USB_NXT | USB2.0 NXT flag |
C17 | GPIO0_IO6 | USB_DATA2 | USB2.0 data line 2 |
C18 | GPIO0_IO7 | USB_DATA3 | USB2.0 data line 3 |
D21 | GPIO0_IO8 | USB_DATA4 | USB2.0 data line 4 |
D20 | GPIO0_IO9 | USB_DATA5 | USB2.0 data line 5 |
E21 | GPIO0_IO10 | USB_DATA6 | USB2.0 data line 6 |
E22 | GPIO0_IO11 | USB_DATA7 | USB2.0 data line 7 |
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