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Ixiasoft
5.9.1. PCI Express
5.9.2. 10/100/1000 Ethernet (HPS)
5.9.3. 10/100/1000 Ethernet (FPGA)
5.9.4. FMC
5.9.5. HPS Shared I/O
5.9.6. USB 2.0 Port (HPS)
5.9.7. RS-232 UART (HPS)
5.9.8. Real-Time Clock (HPS)
5.9.9. SFP+
5.9.10. I2C Interface
5.9.11. FPGA General I/O Configuration
5.9.12. HPS SPIO Interface
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Ixiasoft
5.9.11.1. FPGA-I/O MAX V Interface
Thirteen FPGA I/O pairs (FPGAIO_NP signals) are connected to FPGA I/O MAX V CPLD for Ethernet, FPGA User IOs, Display port, and SDI applications support.
Bank | Pin Number | Schematic Signal Name |
---|---|---|
3E | M2 | FPGAIO9_N |
3E | M1 | FPGAIO9_P |
3E | N4 | FPGAIO8_N |
3E | N3 | FPGAIO8_P |
3E | R3 | FPGAIO7_N |
3E | R2 | FPGAIO7_P |
3E | N2 | FPGAIO6_N |
3E | N1 | FPGAIO6_P |
3E | R1 | FPGAIO5_N |
3E | P1 | FPGAIO5_P |
3E | P4 | FPGAIO4_N |
3E | P3 | FPGAIO4_P |
3E | P6 | FPGAIO3_N |
3E | P5 | FPGAIO3_P |
3E | T5 | FPGAIO2_N |
3E | R5 | FPGAIO2_P |
2I | AR22 | FPGAIO_N |
2I | AR23 | FPGAIO_P |
2I | AL22 | FPGAIO12_N |
2I | AM22 | FPGAIO12_P |
2I | AP21 | FPGAIO11_N |
2I | AR21 | FPGAIO11_P |
2I | AN22 | FPGAIO10_N |
2I | AN21 | FPGAIO10_P |
2I | AL20 | FPGAIO1_N |
2I | AM21 | FPGAIO1_P |
The figure below illustrates the signal connections between two MAX Vs and FPGA.
Figure 29. Control Signals Connection
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