Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.9.11.1. FPGA-I/O MAX V Interface

Thirteen FPGA I/O pairs (FPGAIO_NP signals) are connected to FPGA I/O MAX V CPLD for Ethernet, FPGA User IOs, Display port, and SDI applications support.

Table 42.  I/O Assignments of FPGA I/O Pairs
Bank Pin Number Schematic Signal Name
3E M2 FPGAIO9_N
3E M1 FPGAIO9_P
3E N4 FPGAIO8_N
3E N3 FPGAIO8_P
3E R3 FPGAIO7_N
3E R2 FPGAIO7_P
3E N2 FPGAIO6_N
3E N1 FPGAIO6_P
3E R1 FPGAIO5_N
3E P1 FPGAIO5_P
3E P4 FPGAIO4_N
3E P3 FPGAIO4_P
3E P6 FPGAIO3_N
3E P5 FPGAIO3_P
3E T5 FPGAIO2_N
3E R5 FPGAIO2_P
2I AR22 FPGAIO_N
2I AR23 FPGAIO_P
2I AL22 FPGAIO12_N
2I AM22 FPGAIO12_P
2I AP21 FPGAIO11_N
2I AR21 FPGAIO11_P
2I AN22 FPGAIO10_N
2I AN21 FPGAIO10_P
2I AL20 FPGAIO1_N
2I AM21 FPGAIO1_P

The figure below illustrates the signal connections between two MAX Vs and FPGA.

Figure 29. Control Signals Connection

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