Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.9.3. 10/100/1000 Ethernet (FPGA)

The development board supports two RJ45 10/100/1000 base-T Ethernet using Marvell 88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.

Figure 27. MII Interface between FPGA (MAC) and PHY
Table 32.  Ethernet (FPGA) Pin Assignments
FPGA Pin Assignment Schematic Signal Name Direction Description
AK38 ENETA_TX_N Output Ethernet Port A Transmitter
AK39 ENETA_TX_P Output Ethernet Port A Transmitter
AG32 ENETA_RX_N Input Ethernet Port A Receiver
AG33 ENETA_RX_P Input Ethernet Port A Receiver
AL36 ENETB_TX_N Output Ethernet Port B Transmitter
AL37 ENETB_TX_P Output Ethernet Port B Transmitter
AH34 ENETB_RX_N Input Ethernet Port B Receiver
AH35 ENETB_RX_P Input Ethernet Port B Receiver
AG29 CLK_ENET_FPGA_P Input 125MHz Reference clock from Clock Synthesizer
AG28 CLK_ENET_FPGA_N Input 125MHz Reference clock from Clock Synthesizer

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