Visible to Intel only — GUID: iga1438035869267
Ixiasoft
5.9.1. PCI Express
5.9.2. 10/100/1000 Ethernet (HPS)
5.9.3. 10/100/1000 Ethernet (FPGA)
5.9.4. FMC
5.9.5. HPS Shared I/O
5.9.6. USB 2.0 Port (HPS)
5.9.7. RS-232 UART (HPS)
5.9.8. Real-Time Clock (HPS)
5.9.9. SFP+
5.9.10. I2C Interface
5.9.11. FPGA General I/O Configuration
5.9.12. HPS SPIO Interface
Visible to Intel only — GUID: iga1438035869267
Ixiasoft
5.9.3. 10/100/1000 Ethernet (FPGA)
The development board supports two RJ45 10/100/1000 base-T Ethernet using Marvell 88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.
Figure 27. MII Interface between FPGA (MAC) and PHY
FPGA Pin Assignment | Schematic Signal Name | Direction | Description |
---|---|---|---|
AK38 | ENETA_TX_N | Output | Ethernet Port A Transmitter |
AK39 | ENETA_TX_P | Output | Ethernet Port A Transmitter |
AG32 | ENETA_RX_N | Input | Ethernet Port A Receiver |
AG33 | ENETA_RX_P | Input | Ethernet Port A Receiver |
AL36 | ENETB_TX_N | Output | Ethernet Port B Transmitter |
AL37 | ENETB_TX_P | Output | Ethernet Port B Transmitter |
AH34 | ENETB_RX_N | Input | Ethernet Port B Receiver |
AH35 | ENETB_RX_P | Input | Ethernet Port B Receiver |
AG29 | CLK_ENET_FPGA_P | Input | 125MHz Reference clock from Clock Synthesizer |
AG28 | CLK_ENET_FPGA_N | Input | 125MHz Reference clock from Clock Synthesizer |
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