Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
Document Table of Contents

5.7. General User Input/Output

All user-defined push buttons, DIP switches and LEDs are connected to the MAX V System Controller. The IO_MUX CPLD maps user-defined signals to FPGA I/Os as defined in the GHRD. The following section describes the mapping table.

Table 28.  I/O MAX V Application Modes
User DIP Switch [3:0] Description
0000 Default FPGA mode
0001 Reserve
0010 Reserve
0011 Reserve
0100 Reserve
0101 Reserve
0110 Reserve
0111 Reserve
1000 SDI mode
1001 DP_mode
1010 PCIE EP mode
1011 Reserve
1100 Reserve
1101 Reserve
1110 Reserve
1111 Reserve

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