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5.9.1. PCI Express
5.9.2. 10/100/1000 Ethernet (HPS)
5.9.3. 10/100/1000 Ethernet (FPGA)
5.9.4. FMC
5.9.5. HPS Shared I/O
5.9.6. USB 2.0 Port (HPS)
5.9.7. RS-232 UART (HPS)
5.9.8. Real-Time Clock (HPS)
5.9.9. SFP+
5.9.10. I2C Interface
5.9.11. FPGA General I/O Configuration
5.9.12. HPS SPIO Interface
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5.7. General User Input/Output
All user-defined push buttons, DIP switches and LEDs are connected to the MAX V System Controller. The IO_MUX CPLD maps user-defined signals to FPGA I/Os as defined in the GHRD. The following section describes the mapping table.
User DIP Switch [3:0] | Description |
---|---|
0000 | Default FPGA mode |
0001 | Reserve |
0010 | Reserve |
0011 | Reserve |
0100 | Reserve |
0101 | Reserve |
0110 | Reserve |
0111 | Reserve |
1000 | SDI mode |
1001 | DP_mode |
1010 | PCIE EP mode |
1011 | Reserve |
1100 | Reserve |
1101 | Reserve |
1110 | Reserve |
1111 | Reserve |