Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
Document Table of Contents

4.4.11. The Power Monitor

The Power Monitor measures and reports current power information and communicates with the MAX V device on the board through the JTAG bus. A power monitor circuit attached to the MAX V device allows you to measure the power that the FPGA is consuming.
To start the application, click the Power Monitor icon in the Board Test System application. You can also run the Power Monitor as a stand-alone application. The PowerMonitor.exe resides in the <Package Root Dir>\examples\board_test_system directory.
Note: You cannot run the stand-alone power application and the BTS application at the same time. Also, you cannot run power and clock interface at the same time.
Figure 20. Power Monitor Interface
Control Description
Test Settings Displays the following controls:

Power Rail—Indicates the currently-selected power rail. After selecting the desired rail, click Reset to refresh the screen with updated board readings.

Scale—Specifies the amount to scale the power graph. Select a smaller number to zoom in to see finer detail. Select a larger number to zoom out to see the entire range of recorded values.

Speed—Specifies how often to refresh the graph.

Power Information Displays root-mean-square (RMS) current, maximum, and minimum numerical power readings in mA.
Graph Displays the mA power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. The yellow line indicates the minimum value read since the last reset.
General Information Displays MAX V version and current temperature of the FPGA and board.
Reset Clears the graph, resets the minimum and maximum values, and restarts the Power Monitor.

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