Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.9.11.6. FPGA Auxiliary Signals

Table 49.  FPGA Auxiliary Signals
BANK Pin number Schematic Name Description
2A AH18 PS_D0 PS mode data line
2A AN18 CLK_50M_FPGA MAXV 50Mhz clock
2A AP20 CLKUSR 100Mhz clock
2A AR20 FPGA_IO1 EMAC1 MDC signal
2A AV16 FPGA_IO0 EMAC1 MDIO signal
2A AW16 PCIE1V8_PERSTn PCIE PHY 0 reset signal
2A AV18 PCIE1V8_PERST1n PCIE PHY 1 reset signal
2A AV17 FPGA_IO3 EMAC2 MDC signal
2A AV22 CVP_CONFDONE HPS UART0 TX after FPGA configuration
2A AW20 FPGA_IO2 EMAC2 MDIO signal
2A AU21 CRCERROR HPS UART0 RX after FPGA configuration
2I AT22 DP_AUX_CH_N Display port AUX port N
2I AU22 DP_AUX_CH_P Display port AUX port P

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