Arria® 10 SX SoC Development Kit User Guide

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ID 683227
Date 11/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 SX SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Development Kit Components 6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 SX SoC Development Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC FPGA Embedded Development Suite (EDS) 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver 2.3.5. SD Card Image with Example Software
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Development Kit Components x
5.1. Board Overview 5.2. Featured Device: Arria® 10 SX SoC 5.3. MAX® V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over Onboard Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. Onboard Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe* 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughter Cards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 SX SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Development Kit Components
6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide
A. Safety and Regulatory Compliance Information

5.9.12. HPS SPIO Interface

The HPS can monitor and control the following functional signals through the SPI interface:

  • HPS LED signals
  • HPS push button and DIP switch signals
  • Power good and present signals
  • Reset signals
  • FMCA/B PCIe* power enable signals
  • SFP+ control signals
  • I2C master indication signal
  • HPS warm reset signals
  • PMBus control signals
Table 48.  SPI Interface Pin Definition
Pin Description Function
nCS Chip Select

Active low signal that enables the slave device to receive or transfer data from the master device.
SCK Serial Clock The clock signal produced from the master device to synchronize the data transfer.
MOSI Serial Data Input

Receives data serially at the positive SCK clock.
MISO Serial Data output

Transmits data serially at the negative SCK clock edge.

The HPS SPI controller is the SPI master, and the MAX V works as a slave SPI I/O expander. The SPI interface uses 8-bit frame size. For MOSI, the first byte is used as an instruction byte. Bit [7:1] is the register address. Bit [0] is the operation flag where logic '1' is read flag and logic '0' is the write flag. The second byte is the data byte. For MISO, the first byte are zero byte (pad), second byte is the data byte.

Figure 39. HPS SPI Controller Write Timing Diagram
Figure 40. HPS SPI Write Timing (Write/Write)
Figure 41. HPS SPI Read Timing Diagram
Figure 42. HPS SPI Read Timing (Read/Write)
Figure 43. HPS SPI Read Timing (Read/Read)

16 8-bit registers are implemented. For MOSI, the first byte is used as an instruction byte. Bit [7:1] is the register address. Bit [0] is the operation flag: Logic one is read flag. Logic zero is write flag. Second byte is data byte. For MISO, the first byte are zero byte (pad), second byte is data byte.

Table 49.  SPI I/O Expander Register Definition
Instruction (8 bits) Instruction Description Register Data Description
00000001 CPLD Revision Value

Register 0. Read-only register.

The read value is the CPLD revision value.
00000010 Write HPS LED Registers

Register 1

  • Bit[7:4]—USER_LED_HPS[3:0], Active low, default value is 0xF.
  • Bit[3:0]—Reserved, default value is 0x0.
00000011 Read HPS LED registers

Register 1

  • Bit[7:4]—USER_LED_HPS[3:0]
  • Bit[3:0]—Reserved, default value is 0xF0
00000101 Read HPS push button and DIP switch registers

Register 2. Current status of USER_PB_HPS and USER_DIPSW_HPS.

  • Bit[7:4]—USER_PB_HPS [3:0]
  • Bit[3:0]—USER_DIPSW_HPS [3:0]
00000110 Write HPS push button IRQ flag clear registers

Register 3

  • Bit[7]—Writes logic one to clear bit 7 flag in register 2, writes logic zero to reset this bit after the flag is cleared
  • Bit[6]—Writes logic one to clear bit 6 flag in register 2, writes logic zero to reset this bit after the flag is cleared
  • Bit[5]—Writes logic one to clear bit 5 flag in register 2, writes logic zero to reset this bit after the flag is cleared
  • Bit[4]—Writes logic one to clear bit 4 flag in register 2, writes logic zero to reset this bit after the flag is cleared
00000111 Read HPS push button IRQ flag registers

Register 3. Read-only register.

  • Bit[7:4]—USER_PB_HPS hold registers bits
  • Bit 7—USER_PB_HPS3 IRQ Flag, active low, clear flag by register 3 bit 7
  • Bit 6—USER_PB_HPS2 IRQ Flag, active low, clear flag by register3 bit 6
  • Bit 5—USER_PB_HPS1 IRQ Flag, active low, clear flag by register3 bit 5
  • Bit 4—USER_PB_HPS0 IRQ Flag, active low, clear flag by register3 bit 4
  • Bit[3:0]—Reserved

If one of the push buttons is pressed, the corresponding PB's IRQ register bit is set and A10_SH_GPIO0 is configured to '0'.

The A10_SH_GPIO0 returns to '1' after the HPS clears the associated bit (even if the PB is still held down).

If the second push button is pressed while the HPS is handling the first push button interrupt, the second PB's IRQ register bit remains as a '0' until HPS clears the interrupt. A10_SH_GPIO0 stays low until the HPS clears the second PB's IRQ register bit.
00001001 Read Power good1 registers

Register 4. Read-only register.

  • Bit[7]—operation_flag
    • '1': Power on finished.
    • '0': The system is in power down cycle
  • Bit[6]—1V8_Pgood
    • '1': 1.8 V power rail output is normal
    • '0': 1.8 V power rail output is abnormal
  • Bit[5]—2V5_Pgood
    • '1': 2.5 V power rail output is normal
    • '0': 2.5 V power rail output is abnormal
  • Bit[4]—3V3_Pgood
    • '1': 3.3 V power rail output is normal
    • '0': 3.3 V power rail output is abnormal
  • Bit[3]—5V0_Pgood
    • '1': 5 V power rail output is normal
    • '0': 5 V power rail output is abnormal
  • Bit[2]—0V9_Pgood
    • '1': 0.9 V power rail output is normal
    • '0': 0.9 V power rail output is abnormal
  • Bit[1]—0V95_Pgood
    • '1': 0.95 V power rail output is normal
    • '0': 0.95 V power rail output is abnormal
  • Bit[0]—1V0_Pgood
    • '1': 1.0 V power rail output is normal
    • '0': 1.0 V power rail output is abnormal
00001011 Read Power good2 registers
Register 5. Read-only register.
  • Bit[7]—HPS_Pgood
    • '1': HPS core power rail output is normal
    • '0': HPS core power rail output is abnormal
  • Bit[6]—HILOHPS_VDDPgood
    • '1': HPS memory power rail output is normal
    • '0': HPS memory power rail output is abnormal
  • Bit[5]—HILO_VDDPgood
    • '1': FPGA memory VDD power rail output is normal
    • ‘0’: FPGA memory VDD power rail output is abnormal
  • Bit[4]—HILO_VDDQPgood
    • '1': FPGA memory VDDQ power rail output is normal
    • '0': FPGA memory VDDQ power rail output is abnormal
  • Bit[3]—FMCAVADJPGood
    • '1': FMCAVADJ power rail output is normal.
    • '0': FMCAVADJ power rail output is abnormal
  • Bit[2]—FMCBVADJPGood
    • '1': FMCBVADJ power rail output is normal
    • '0': FMCBVADJ power rail output is abnormal
  • Bit[1]—FAC2MPgood
    • '1': FMCA slot powers are normal
    • '0': FMCA slot powers are abnormal
  • Bit[0]—FBC2MPgood
    • '1': FMCB slot powers are normal
    • '0': FMCB slot powers are abnormal
00001101 Read Power good3 and present registers

Register 6. Read-only register.

  • Bit[7]—FAM2CPgood
    • '1': FMCA slot DC power outputs are normal
    • '0': FMCA slot DC power outputs are abnormal
  • Bit[6]—10V_Fail_n
    • '1'’: Input voltage is above 10 V.
    • '0': Input voltage is below 10 V
  • Bit[5]—BF_PRESENTn
    • '1': No boot flash card
    • '0': Boot flash present
  • Bit[4]—FILE_PRESENTn
    • '1': No file flash card
    • '0': File flash present
  • Bit[3]—FMCA_PRESENTn
    • '1': No FMCA card
    • '0': FMCA card present
  • Bit[2]—FMCB_PRESENTn
    • '1': No FMCB card
    • '0': FMCB present
  • Bit[1]—PCIE_PRESENTn
    • '1': No PCIe* card
    • '0': PCIe* card present
  • Bit[0]—Reserved
00001110 Write FMCA/B PCIe* power enable registers

Register 7

  • Bit[7]—PCIE_EN
    • '1': Enable PCIe* RC slot power
    • '0': Disable PCIe* RC slot power
  • Bit[6]—PCIE_AUXEN
    • '1': Enable PCIe* RC slot auxiliary power
    • '0': Disable PCIe* RC auxiliary power
  • Bit[5:0]—Reserved
00001111 Read FMCA/B PCIe* power enable registers

Register 7

Reads the status of power enable register.
00010000 Write HPS resets registers

Register 8

  • Bit[7]—Reserved
  • Bit[6]—Reserved
  • Bit[5]—Reserved
  • Bit[4]—Reserved
  • Bit[3]—Reserved
  • Bit[2]—Reserved
  • Bit[1]—ENET_HPS_RESETn. Active low to reset the HPS Ethernet port.
  • Bit[0]—Reserved
00010001 Read HPS reset registers

Register 8

  • Bit[7]—HPS_UARTA_RESETn. Read-only bit. Always '1'.
  • Bit[6]—HPS_WARM_RESETn. Read-only bit.
    • '0': WARM_Reset push button is pressed
    • '1': No action
  • Bit[5]—HPS_WARM_RESET1n. Read - only bit.
    • '0': Trace reset is detected
    • '1': No action
  • Bit[4]—HPS_COLD_RESETn. Read-only bit.
    • '0': Cold_Reset push button is pressed
    • '1': No action
  • Bit[3]—HPS_NPOR. Read-only, NPOR for HPS, active low.
  • Bit[2]—HPS_NRST. Read-only, NRST for HPS, active low.
  • Bit[1]—ENET_HPS_RESETn. Read the status of ENET_HPS_RESETn.
  • Bit[0]—ENET_HPS_INTn. ENET_HPS_INTn current status.
00010010 Write USB & BQSPI & FILE & PCIE resets registers

Register 9

  • Bit[7]—USB_RESET. Active high to reset the HPS USB
  • Bit[6]—BQSPI_RESETn. Active low to reset the boot flash
  • Bit[5]—FILE_RESETn. Active low to reset the FILE flash
  • Bit[4]—PCIE_PERSTn. Active low to reset the PCIE slot
  • Bit[3:0]—Reserved
00010011 Read USB & BQSPI & FILE & PCIE resets registers

Register 9

Reads the status of USB & BQSPI & FILE & PCIE resets.

  • Bit[7]—USB_RESET
  • Bit[6]—BQSPI_RESETn
  • Bit[5]—FILE_RESETn
  • Bit[4]—PCIE_RESETn
  • Bit[3:0]—Reserved
00010100 Write SFPA control registers

Register 10

  • Bit[7]—SFPA_TXDISABLE
    • '1': Disable SFPA TX
    • '0': Enable SFPA TX
  • Bit[6:5]—SFPA_RATESEL[1:0]. SFPA RX rate selection.
    • '0': < 4.25 GBd
    • '1': > 4.25 GBd
  • Bit[4:0]—Reserved
00010101 Read SFPA control registers

Register 10

  • Bit[7]—SFPA_TXDISABLE.
    • '1': Disable SFPA TX
    • '0': Enable SFPA TX
  • Bit[6:5]—SFPA_RATESEL[1:0]. SFPA RX rate selection.
    • '0': < 4.25 GBd
    • '1': > 4.25 GBd
  • Bit[4]—SFPA_LOS. Loss signal of SFPA.
    • '1': LOS
    • '0': Normal
  • Bit[3]—SFPA_FAULT. Tx fault signal of SFPA.
    • '1': Fault
    • '0': Normal
  • Bit[2]—SFPA_PRESENTn. Detect signal of SFP module in slot A.
    • '1': No SFP module
    • '0': SFP module present
  • Bit[1:0]—Reserved
00010110 Write SFPB control registers

Register 11

  • Bit[7]—SFPB_TXDISABLE.
    • '1': Disable SFPB TX
    • '0': Enable SFPB TX
  • Bit[6:5]—SFPA_RATESEL[1:0]. SFPA RX rate selection.
    • '0': < 4.25 GBd
    • '1': > 4.25 GBd
  • Bit[4:0]—Reserved
00010111 Read SFPB control registers

Register 11

  • Bit[7]—SFPB_TXDISABLE. Reads the status of SFPB TXDISABLE.
  • Bit[6:5]—SFPB_RATESEL[1:0]. Reads the status of SFPB rate selection.
  • Bit[4]—SFPB_LOS. Reads the Los signal of SFPB.
    • '1': Loss
    • '0': Normal
  • Bit[3]—SFPB_FAULT. Reads the Tx Fault signal of SFPB.
    • '1': Fault
    • '0': Normal
  • Bit[2]—SFPB_PRESENTn. Detects signal of SFP module in slot B.
    • '1': no SFP module
    • '0': SFP module present
  • Bit[1:0]—Reserved
00011001 Read I2C master register

Register 12

  • Bit[7]—I2C master indication
    • '1': HPS is the I2C master
    • '0': MAX® V is the I2C master
  • Bit[6:0]—Reserved
00011010 Write HPS warm reset register

Register 13

  • Bit[7:6]—"00"
  • Bit[5]—HPS_SPI_WARM_RESETn. Active low to warm reset HPS; MAX® V automatically clears this bit 1 us after it becomes active.
  • Bit[4:0]—"00000"
00011011 Read HPS warm reset register

Register 13

  • Bit[7:6]—"00"
  • Bit[5]—HPS_SPI_WARM_RESETn. Reads the status of the HPS SPI warm reset.
  • Bit[4:0]—"00000"
00011100 Write HPS warm reset key register

Register 14

Bit[7:0]—key register of HPS warm reset. Value of 0xA8 allows bit5 in register 13 to be recognized.

Software must write a different value to this register after a valid write to bit5 in register 13.
00011101 Read HPS warm reset key register

Register 14

Value currently in HPS warm reset key register.
00011110 Write PMBus control register

Register 15

  • Bit[7]—A10PMBUSEN
    • '1': Enable the Arria® 10 FPGA PMBUS
    • '0': Disable the Arria® 10 FPGA PMBUS
  • Bit[6]—A10_PMBUSDIS_N.
    • '1': Enable the system MAX® V/HPS PMBus.
    • '0': Disable the system MAX® V/HPS PMBus.
  • Bit[5:0]—Reserved
00011111 Read PMBus control register

Register 15

  • Bit[7]—A10PMBUSEN.
    • '1': The Arria® 10 FPGA PMBUS is enabled.
    • '0: The Arria® 10 FPGA PMBUS is disabled
  • Bit[6]—A10_PMBUSDIS_N
    • '1': The system MAX® V/HPS PMBus is enabled
    • '0': The system MAX® V/HPS PMBus is disabled
  • Bit[5]—Pmbus_Altertn.
    • '1': I2C is normal.
    • '0': I2C hangs
  • Bit[4:0]—Reserved
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