Arria® 10 SX SoC Development Kit User Guide

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ID 683227
Date 11/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 SX SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Development Kit Components 6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 SX SoC Development Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC FPGA Embedded Development Suite (EDS) 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver 2.3.5. SD Card Image with Example Software
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Development Kit Components x
5.1. Board Overview 5.2. Featured Device: Arria® 10 SX SoC 5.3. MAX® V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over Onboard Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. Onboard Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe* 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughter Cards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 SX SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Development Kit Components
6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide
A. Safety and Regulatory Compliance Information

1.2. Feature Summary

The development board features the following major component blocks:

  • Arria® 10 SX SoC (10AS066N3F40E2SG) in a 1517-pin FBGA (FineLine Ball-Grid Array) package
  • FPGA configuration circuitry
    • Active Serial (AS) ×1 or ×4 configuration (EPCQ1024L)
    • MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the system controller
    • MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the I/O multiplier CPLD
  • Clocking circuitry
    • SI5338 programmable oscillator
    • LMK04828 clock cleaner
    • HPS clock options: 25 MHz, 33 MHz, and SMA input (2V5 LVCMOS)
    • SI5112 100 MHz clock generator for PCI Express* interface
    • SI516 148.5 MHz voltage control oscillator for SDI interface
  • Supported memory
    • HPS memory size (HILO card):
      • 2 GB DDR3 (256 Mb × 40 × dual rank)
      • 1 GB DDR3 (256 Mb × 40 × single rank)
      • 1 GB DDR4 (256 Mb × 40 × single rank)—ships with kit
    • FPGA memory size (HILO Card):
      • 4 GB DDR3 (256 Mb × 72 × dual rank)
      • 2 GB DDR3 (256 Mb × 72 × single rank)
      • 2 GB DDR4 (256 Mb × 72 × single rank)—ships with kit
      • 16 MB QDRV (4 Mb × 36)
      • 128 MB RLDRAM3 (16 Mb × 72)
    • HPS boot flash (flash card):
      • NAND flash (x8): 128 MB (MT29F1G08ABBEAH4)—ships with kit
      • QSPI flash: 128 MB (MT25QU01GBBA8E12-0SIT)—ships with kit
      • SD Micro flash card: 4 GB (Kingston)—ships with kit
    • Optional FPGA file flash (flash card):
      • NAND flash (×8): 128 MB (MT29F1G08ABBEAH4)
      • QSPI flash: 128 MB (MT25QU01GBBA8E12-0SIT)
      • SD Micro flash card: 4 GB (Kingston)
  • Communication ports
    • HPS communication ports:
      • USB 2.0 port (PHY PN: USB3320C-EZK)
      • RGMII 10/100/1000 Ethernet port (PHY PN: KSZ9031RNXCA)
      • USB-UART port (FT232R)
      • DB-9 RS-232 Port (MAX3221)
      • I2C port (I2C1 of shared I/O bit 12 and 13)
    • FPGA I/O connections:
      • FPGA V57.1 High Pin Count FMC slot
      • FPGA Altera Low Pin Count FMC slot
      • FMC_ PCIe* 2.0 ×8 EP cable
      • FPGA PCIe* 1.0/2.0/3.0 ×8 RC slot
    • FPGA communication ports:
      • 2× SGMII Gigabit Ethernet ports (PHY PN: 88E1111-B2-NDC2C000)
      • 2× 10Gb/s SFP+ ports
      • Display port (DP)
      • SDI/SDO video port
      • SPI port
      • UART port
    • FPGA debug ports:
      • 16-bit Trace port (FPGA Trace)
  • General user I/O
    • LEDs and displays
      • 4× FPGA user LEDs
      • 4× HPS user LEDs
      • Configuration load LED
      • Configuration done LED
      • Error LED
      • 3× configuration select LEDs
      • 4× onboard Intel® FPGA Download Cable II status LEDs
      • 2× FMC interface LEDs
      • 2× UART data transmit and receive LEDs
      • Power on LED
      • Two-line character LCD display
    • Push buttons
      • CPU cold reset push button and one CPU warm reset push button
      • Logic reset push button
      • Program select push button
      • Program configuration push button
      • 4× FPGA user push buttons
      • 4× HPS user push buttons
      • External interrupt push button
    • DIP switches
      • JTAG chain control DIP switch
      • Board settings DIP switch
      • FPGA configuration mode DIP switch
      • General user DIP switch
    • Power supply
      • 12 V DC Input
    • Mechanical
      • 7.175" x 9.3" rectangular form factor
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