Intel® Arria® 10 SoC Development Kit User Guide

ID 683227
Date 7/12/2023
Public
Document Table of Contents

5.6.2. JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW3) either removes or includes devices in the active JTAG chain.

The SW3 switch select controls the JTAG master/slave select. The DIP switch MSTR switches control the master select. The other 5 pins are bypass pins for the various available JTAG slaves. The following slaves are available and can be bypassed by moving the corresponding bypass switch to the 'ON' position.

Table 24.  JTAG Configuration Modes
Switch 3 Bit Board Label Function
1 Arria 10

ON- Arria10 JTAG Bypass

OFF- Arria10 JTAG Enable

2 I/O MAX V

ON- MAXV JTAG Bypass

OFF- MAXV JTAG Enable

3 FMCA

ON- FMCA JTAG Bypass

OFF- FMCA JTAG Enable

4 FMCB

ON- FMCB JTAG Bypass

OFF- FMCB JTAG Enable

5 PCIe

ON- PCIe JTAG Bypass

OFF- PCIe JTAG Enable

6 MSTR[0] Refer to Table 25
7 MSTR[1] Refer to Table 25
8 MSTR[2] Refer to Table 25

The MSTR switch settings and their meanings can be seen in the table below.

Table 25.  Modes for Master Switches
MSTR2 MSTR1 MSTR0 Modes
ON ON ON BOOT
OFF ON ON FMCA JTAG Master
ON OFF ON FMCB JTAG Master
ON ON OFF FTRACE JTAG Master
OFF OFF OFF On-Board USB-Blaster II JTAG Master
ON OFF OFF System Configuration Mode
OFF ON OFF GUI Test Mode
OFF OFF ON Reserved

The bypass switch settings dictate which slaves are in/out of the chain, but see below for the order if all were enabled in the chain.

  1. Arria 10
  2. IO_MAXV
  3. PCIe
  4. FMCA
  5. FMCB

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