Intel® Arria® 10 SoC Development Kit User Guide

ID 683227
Date 7/12/2023
Document Table of Contents

5.4. Configuration

This section describes the FPGA, I/O MUX CPLD, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria 10 SoC development board.

The Arria 10 SoC development board supports the following configuration methods using JTAG:

  • On-board USB-Blaster II is the default method for configuring the FPGA using the Quartus Prime Programmer in JTAG mode with the supplied USB cable.
  • External Mictor connector for configuring the HPS using the ARM DS-5 Altera Edition software and DSTREAM or JTAG debug and trace tools such as Lauterbach TRACE32.
  • External USB-Blaster for configuring the FPGA when you connect the external USB-Blaster to the JTAG header (J24).

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