Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
Public
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Document Table of Contents
Document Table of Contents
1. Arria 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components A. Additional Information
1. Arria 10 SoC Development Kit Overview
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Quartus Prime Design Software 2.3. Installing the Altera SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the USB-Blaster Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Quartus Prime Design Software
2.2.1. Activating Your License
3. Development Board Setup
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components
5.1. Board Overview 5.2. Featured Device: Arria 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board USB-Blaster II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External USB-Blaster
5.6. Setup Elements
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output
5.7.1. Character LCD
5.8. Clock Circuitry
5.8.1. On-Board Oscillators
5.9. Components and Interfaces
5.9.1. PCI Express 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements
A.2.1. CE EMI Conformity Caution
1. Arria 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
A. Additional Information

4.4.1. Using the Configure Menu

Use the Configure menu to select the design you want to use. Each design example tests different board features. Choose a design from this menu and the corresponding tabs become active for testing.
Figure 9. The Configure Menu

To configure the FPGA with a test system design, perform the following steps:

  1. On the Configure menu, click the configure command that corresponds to the functionality you wish to test.
  2. In the dialog box that appears, click Configure to download the corresponding design to the FPGA.
    Figure 10. Programmer Dialog Window
Level Two Title

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