Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
Public
Download
Document Table of Contents

5.10.2. HPS External Memory

A 40-bit HPS DDR3/4 memory interface (32-bit data and 8-bit ECC data) assigned to FPGA 2K and 2J I/O banks is connected to a HILO memory daughtercard.

Table 53.  Bank 2K and 2J I/O Pin Assignments for DDR3 and DDR4 Interface
BANK Pin Number DDR3 Interface DDR4 Interface Schematic Name
2K P25 DM4 DM4 HMEM_DQ_ADDR_CMD0
2K N25 DQ4 bit DQ4 bit HMEM_DQ_ADDR_CMD3
2K L26 DQ4 bit DQ4 bit HMEM_DQ_ADDR_CMD4
2K K26 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD2
2K M25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD1
2K L25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD5
2K L24 DQS4_n DQS4_n HMEM_DQS_ADDR_CMD_N
2K K25 DQS4_p DQS4_P HMEM_DQS_ADDR_CMD_P
2K N24 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD6
2K M24 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD7
2K J25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD8
2K J26
2K J24 BA2 BG0 HMEM_ADDR_CMD18
2K H24 BA1 BA1 HMEM_ADDR_CMD17
2K E25 BA0 BA0 HMEM_ADDR_CMD16
2K D25 CASn A17 HMEM_ADDR_CMD19
2K F23 RASn A16 HMEM_ADDR_CMD26
2K F24 A15 A15 HMEM_ADDR_CMD15
2K G25 A14 A14 HMEM_ADDR_CMD14
2K G26 A13 A13 HMEM_ADDR_CMD13
2K F26 A12 A12 HMEM_ADDR_CMD12
2K E26 240 ohm reference resistor 240 ohm reference resistor RZQ_2K
2K G24 133Mhz DDR reference clock 133Mhz DDR reference clock CLK_HPSEMI_N
2K F25 133Mhz DDR reference clock 133Mhz DDR reference clock CLK_HPSEMI_P
2K D24 A11 A11 HMEM_ADDR_CMD11
2K C24 A10 A10 HMEM_ADDR_CMD10
2K E23 A9 A9 HMEM_ADDR_CMD9
2K D23 A8 A8 HMEM_ADDR_CMD8
2K C23 A7 A7 HMEM_ADDR_CMD7
2K B22 A6 A6 HMEM_ADDR_CMD6
2K B24 A5 A5 HMEM_ADDR_CMD5
2K C25 A4 A4 HMEM_ADDR_CMD4
2K C21 A3 A3 HMEM_ADDR_CMD3
2K C22 A2 A2 HMEM_ADDR_CMD2
2K C26 A1 A1 HMEM_ADDR_CMD1
2K B26 A0 A0 HMEM_ADDR_CMD0
2K A18 No use PAR HMEM_ADDR_CMD31
2K A17 No use CSN1 HMEM_ADDR_CMD30
2K B19 DDR3 interface clock DDR4 interface clock

HMEM_CLK_N

2K B20 DDR3 interface clock DDR4 interface clock HMEM_CLK_P
2K A23 ClKe1 CKe1 HMEM_ADDR_CMD21
2K A24 CKe0 CKe0 HMEM_ADDR_CMD20
2K A25 ODT1 ODT1 HMEM_ADDR_CMD25
2K A26 ODT0 ODT0 HMEM_ADDR_CMD24
2K B21 CSn1 ACTn HMEM_ADDR_CMD23
2K A22 CSn0 CSn0 HMEM_ADDR_CMD22
2K A19 Resetn Resetn HMEM_ADDR_CMD27
2K A20 Wen BG1 HMEM_ADDR_CMD28
2J AV26 DM3 DM3 HPSMEM_DMA0
2J AV27 DQ3 bit DQ3 bit HMEM_DQA4
2J AU27 DQ3 bit DQ3 bit HMEM_DQA5
2J AU28 DQ3 bit DQ3 bit HMEM_DQA6
2J AV28 DQ3 bit DQ3 bit HMEM_DQA1
2J AW28 DQ3 bit DQ3 bit HMEM_DQA0
2J AW25 DQS 3n DQS_n3 HMEM_DQSA_N0
2J AW26 DQS 3p DQS _p3 HMEM_DQSA_P0
2J AV24 DQ3 bit DQ3 bit HMEM_DQA2
2J AW24 DQ3 bit DQ3 bit HMEM_DQA3
2J AV23 DQ3 bit DQ3 bit HMEM_DQA7
2J AW23
2J AU25 DM2 DM2 HPSMEM_DMA1
2J AU26 DQ2 bit DQ2 bit HMEM_DQA8
2J AR26 DQ2 bit DQ2 bit HMEM_DQA11
2J AT26 DQ2 bit DQ2 bit HMEM_DQA10
2J AT23 DQ2 bit DQ2 bit HMEM_DQA14
2J AU24 DQ2 bit DQ2 bit HMEM_DQA12
2J AT24 DQS2n DQS_n2 HMEM_DQSA_N1
2J AT25 DQS2p DQS_p2 HMEM_DQSA_P1
2J AP25 DQ2 bit DQ2 bit HMEM_DQA13
2J AR25 DQ2 bit DQ2 bit HMEM_DQA9
2J AP23 DQ2 bit DQ2 bit HMEM_DQA15
2J AP24
2J AN26 DM1 DM1 HPSMEM_DMA2
2J AP26 DQ1 bit DQ1 bit HMEM_DQA22
2J AN23 DQ1 bit DQ1 bit HMEM_DQA17
2J AN24 DQ1 bit DQ1 bit HMEM_DQA18
2J AK26 DQ1 bit DQ1 bit HMEM_DQA19
2J AL26 DQ1 bit DQ1 bit HMEM_DQA16
2J AL25 DQSn1 DQS1n HMEM_DQSA_N2
2J AM25 DQSp1 DQSl1p HMEM_DQSA_P2
2J AK23 DQ1 bit DQ1 bit HMEM_DQA20
2J AL23 DQ1 bit DQ1 bit HMEM_DQA21
2J AM24 DQ1 bit DQ1 bit HMEM_DQA23
2J AL24
2J AH25 DM0 DM0 HPSMEM_DMA3
2J AJ26 DQ0 bit DQ0 bit HMEM_DQA31
2J AH23 DQ0 bit DQ0 bit HMEM_DQA30
2J AH24 DQ0 bit DQ0 bit HMEM_DQA27
2J AJ23 DQ0 bit DQ0 bit HMEM_DQA29
2J AJ24 DQ0 bit DQ0 bit HMEM_DQA28
2J AJ25 DQSn0 DQS0n HMEM_DQSA_N3
2J AK25 DQSp0 DQS0p HMEM_DQSA_P3
2J AF25 DQ0 bit DQ0 bit HMEM_DQA25
2J AG25 DQ0 bit DQ0 bit HMEM_DQA26
2J AF24 DQ0 bit DQ0 bit HMEM_DQA24
2J AG24 No use Alertn HMEM_ADDR_CMD29

Did you find the information on this page useful?

Characters remaining:

Feedback Message