Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.10.1. FPGA External Memory

One 72-bit memory interface connected to a HILO memory card is assigned into three I/O banks (3B, 3C and 3D). A hard memory core is assigned to this interface. The table below lists the memory interface pin assignment of DDR3, DDR4, RLDRAM3 and QDRIV interfaces.

Table 50.  FPGA External Memory Interface Pin Assignment
BANK Pin Number DDR3 DDR4 RLDRAM3 QDRIV Schematic Name
3D W8 DDR3 DQ36 DDR4 DQ36 RLDRAM3 DQ23 QDRIV DQB4 MEM_DQB4
3D Y8 DDR3 DQ32 DDR4 DQ32 RLDRAM3 DQ19 QDRIV DQB0 MEM_DQB0
3D Y10 DDR3 DQ37 DDR4 DQ37 RLDRAM3 DQ24 QDRIV DQB5 MEM_DQB5
3D AA9 DDR3 DQ38 DDR4 DQ38 RLDRAM3 DQ25 QDRIV DQB6 MEM_DQB6
3D AB11 DDR3 DQ33 DDR4 DQ33 RLDRAM3 DQ26 QDRIV QKB_N0 MEM_DQB1
3D AA10 DDR3 DM4 DDR4 LDM_n2 RLDRAM3 DQ18 QDRIV DINVB0 MEM_DMB0
3D AA8 DDr3 DQSn4 DQSL_n2 RLDRAM3 QK2n QDRIV DQB17 MEM_DQSB_N0
3D AA7 DDR3 DQSp4 DQSL_p2 RLDRAM3 QK2p QDRIV DQB16 MEM_DQSB_P0
3D AB10 DDR3 DQB34 DDR4 DQ34 RLDRAM3 DQ21 QDRIV DQB2 MEM_DQB2
3D AB9 DDR3 DQ35 DDR4 DQ35 RLDRAM3 DQ22 QDRIV DQB3 MEM_DQB3
3D AB7 DDR3 DQ39 DDR4 DQ39 RLDRAM3 DQ26 QDRIV QKB_N0 MEM_DQB7
3D AC7 QDRIV QKB_P0 MEM_QKB_P0
3D Y7 DDR3 DQ41 DDR4 DQ41 QDRIV DQB8 MEM_DQB9
3D Y6 DDR3 DQ40 DDR4 DQ40 QDRIV DQB7 MEM_DQB8
3D Y5 DDR3 DQ43 DDR4 DQ43 QDRIV DQB10 MEM_DQB11
3D AA5 DDR3 DQ42 DDR4 DQ42 QDRIV DQB9 MEM_DQB10
3D AD5 DDR3 DQ46 DDR4 DQ46 QDRIV DQB13 MEM_DQB14
3D AD4 DDR3 DQ44 DDR4 DQ44 QDRIV DQB11 MEM_DQB12
3D AE6 DDR3 DQS_n5 DDR4 DQSU_n2 RLDRAM3 DK0n QDRIV DKB_n0 MEM_DQSB_N1
3D AE5 DDR3 DQs_p5 DDR4 DQSU_p2 RLDRAM3 DK0p QDRIV DKB_p0 MEM_DQSB_P1
3D AC6 DDR3 DQ45 DDR4 DQB45 QDRIV DQB12 MEM_DQB13
3D AD6 QDRIV DQB15 MEM_DQB32
3D AB6 DDR3 DQ47 DDR4 DQ47 QDRIV DQB14 MEM_DQB15
3D AB5 DDR3 DM5 DDR4 UDM_n2 QDRIV QVLDB0 MEM_DMB1
3D Y3 DDR3 DQ52 DDR4 DQ52 RLDRAM3 DQ5 QDRIV DQB22 MEM_DQB20
3D Y2 DDR3 DQ54 DDR4 DQ54 RLDRAM3 DQ7 QDRIV DQB24 MEM_DQB22
3D W1 DDR3 DQ49 DDR4 DQ49 RLDRAM3 DQ2 QDRIV DQB19 MEM_DQB17
3D Y1 DDR3 DQ50 DDR4 DQ50 RLDRAM3 DQ3 QDRIV DQB20 MEM_DQB18
3D AA4 DDR3 DQ51 DDR4 DQ51 RLDRAM3 DQ4 QDRIV DQB21 MEM_DQB19
3D AB4 DDR3 DQ48 DDR4 DQ48 RLDRAM3 DQ1 QDRIV DQB18 MEM_DQB16
3D AA3 DDR3 DQS_n6 DDR4 DQSL_n3 RLDRAM3 QK0n QDRIV DQB35 MEM_DQSB_N2
3D AA2 DDR3 DQS_p6 DDR4 DQSL_p3 RLDRAM3 QK0 QDRIV DQB34 MEM_DQSB_P2
3D AB2 DDR3 DM6 DDR4 LDM_n3 RLDRAM3 DQ0 QDRIV DINVB1 MEM_DMB2
3D AB1 DDR3 DQ53 DDR4 DQ53 RLDRAM3 DQ6 QDRIV DQB23 MEM_DQB21
3D AC4 DDR3 DQ55 DDR4 DQ55 RLDRAM3 DQ8 QDRIV QKB_N1 MEM_DQB23
3D AC3 RLDRAM3 DM0 QDRIV QKB_P1 MEM_QKB_P1
3D AC1 DDR3 DM7 DDR4 UDM_n3 QDRIV QVLDB1 MEM_DMB3
3D AD1 DDR3 DQ63 DDR4 DQ63 QDRIV DQB32 MEM_DQB31
3D AD3 DDR3 DQ62 DDR4 DQ62 QDRIV DQB31 MEM_DQB30
3D AC2 QDRIV DQB33 MEM_DQB33
3D AF2 DDR3 DQ61 DDR4 DQ61 QDRIV DQB29 MEM_DQB29
3D AG2 DDR3 DQ60 DDR4 DQ60 QDRIV DQB28 MEM_DQB28
3D AG1 DDR3 DQSn7 DDR4 DQSU_n3 DKB_n1 MEM_DQSB_N3
3D AH1 DDR3 DQSp7 DDR4 DQSU_p3 DKB_P1 MEM_DQSB_P3
3D AE2 DDR3 DQ57 DDR4 DQ57 QDRIV DQB26 MEM_DQB25
3D AE1 DDR3 DQ58 DDR4 DQ58 QDRIV DQB27 MEM_DQB26
3D AE3 DDR3 DQ56 DDR4 DQ56 QDRIV DQB24 MEM_DQB24
3D AF3 DDR3 DQ59 DDR4 DQ59 QDRIV DQB28 MEM_DQB27
3C AC9 DDR3 DQ67 DDR4 DQ67 MEM_DQ_ADDR_CMD4
3C AC8 DDR3 DQ66 DDR4 DQ66 MEM_DQ_ADDR_CMD3
3C AE11 DDR3 DM8 DDR4 LDM_n4 MEM_DQ_ADDR_CMD0
3C AE10 DDR3 DQ65 DDR4 DQ65 MEM_DQ_ADDR_CMD2
3C AD9 DDR3 DQ64 DDR4 DQ64 MEM_DQ_ADDR_CMD1
3C AD8 DDR3 DQ68 DDR4 DQ68 MEM_DQ_ADDR_CMD5
3C AE8 DDR3_DQS8_n DDR4 DQSL_n4 MEM_DQS_ADDR_CMD_N
3C AF8 DDR3_DQS8_p DDR4_DQSL_P4 MEM_DQS_ADDR_CMD_P
3C AC11 DDR3 DQ69 DQ69 MEM_DQ_ADDR_CMD6
3C AD10 DDR3 DQ70 DQ70 MEM_DQ_ADDR_CMD6
3C AF10 DDR3 DQ71 DQ71 MEM_DQ_ADDR_CMD8
3C AF9 DDR4 ALERTn RLDRAM3 Csn3 QDRIV A22 MEM_ADDR_CMD29
3C AG4 DDR3 BA2 DDR4 BG0 RLDRAM3 BA2 QDRIV A21 MEM_ADDR_CMD18
3C AH4 DDR3 BA1 DDR4 BA1 RLDRAM3 BA1 QDRIV A20 MEM_ADDR_CMD17
3C AF5 DDR3 BA0 DDR4 BA0 RLDRAM3 BA0 QDRIV A19 MEM_ADDR_CMD16
3C AF4 CASn DDr4 A17 RLDRAM3 A17 QDRIV A18 MEM_ADDR_CMD19
3C AE7 RASn DDR4 A16 RLDRAM3 A18 QDRIV A17 MEM_ADDR_CMD26
3C AF7 DDR3 A15 DDR4 A15 RLDRAM3 A15 QDRIV A16 MEM_ADDR_CMD15
3C AH3 DDR3 A14 DDR4 A14 RLDRAM3 A14 QDRIV A15 MEM_ADDR_CMD14
3C AJ3 DDR3 A13 DDR4 A13 RLDRAM3 A13 QDRIV A14 MEM_ADDR_CMD13
3C AG7 DDR3 A12 DDR4 A12 RLDRAM3 A12 QDRIV A13 MEM_ADDR_CMD12
3C AH7 240 ohm Reference resistor MEM_ADDR_CMD12
3C AG6 133Mhz Reference clock CLK_EMI_N
3C AG5 133Mhz Reference clock CLK_EMI_P
3C AH6 DDR3 A11 DDR4 A11 RLDRAM3 A11 QDRIV A12 MEM_ADDR_CMD11
3C AJ5 DDR3 A10 DDR4 A10 RLDRAM3 A10 QDRIV A11 MEM_ADDR_CMD10
3C AJ4 DDR3 A9 DDR4 A9 RLDRAM3 A9 QDRIV A10 MEM_ADDR_CMD9
3C AK3 DDR3 A8 DDR4 A8 RLDRAM3 A8 QDRIV A9 MEM_ADDR_CMD8
3C AJ6 DDR3 A7 DDR4 A7 RLDRAM3 A7 QDRIV A8 MEM_ADDR_CMD7
3C AK6 DDR3 A6 DDR4 A6 RLDRAM3 A6 QDRIV A7 MEM_ADDR_CMD6
3C AK5 DDR3 A5 DDR4 A5 RLDRAM3 A5 QDRIV A6 MEM_ADDR_CMD5
3C AL5 DDR3 A4 DDR4 A4 RLDRAM3 A4 QDRIV A5 MEM_ADDR_CMD4
3C AL4 DDR3 A3 DDR4 A3 RLDRAM3 A3 QDRIV A4 MEM_ADDR_CMD3
3C AL3 DDR3 A2 DDR4 A2 RLDRAM3 A2 QDRIV A3 MEM_ADDR_CMD2
3C AM4 DDR3 A1 DDR4 A1 RLDRAM3 A1 QDRIV A2 MEM_ADDR_CMD1
3C AN3 DDR3 A0 DDR4 A0 RLDRAM3 A0 QDRIV A1 MEM_ADDR_CMD0
3C AH2 DDR4 PAR RLDRAM3 REFn QDRIV A0 MEM_ADDR_CMD31
3C AJ1 DDR4 Csn1 RLDRAM3 Csn2 QDRIV AINV MEM_ADDR_CMD30
3C AK2 DDR3 CLKn DDR4 CLKn RLDRAM3 CLKn QDRIV CLKn MEM_CLK_N
3C AK1 DDR3 CLKp DDR4 CLKp RLDRAM3 CLkp QDRIV CLKp MEM_CLK_P
3C AN1 DDR3 CKE1 DDR4 CKE1 RLDRAM3 Wen QDRIV RWBn MEM_ADDR_CMD21
3C AM1 DDR3 CKE0 DDR4 CKE0 RLDRAM3 A20 QDRIV RWAn MEM_ADDR_CMD20
3C AR2 DDR3 ODT1 DDR4 ODT1 RLDRAM3 A19 QDRIV LDBn MEM_ADDR_CMD25
3C AR1 DDR3 ODT0 DDR4 ODT0 RLDRAM3 A18 QDRIV LDAn MEM_ADDR_CMD24
3C AL2 DDR3 Csn1 DDR4 Actn RLDRAM3 CSn1 QDRIV LBK1n MEM_ADDR_CMD23
3C AM2 DDR3 Csn0 DDR4 Csn0 RLDRAM3 CSn0 QDRIV LDBn MEM_ADDR_CMD22
3C AN2 DDR3 resetn DDR4 resetn RLDRAM3 resetn QDRIV resetn MEM_ADDR_CMD27
3C AP1 DDR3 Wen DDR4 BG1 RLDRAM3 BA3 QDRIV CFGn MEM_ADDR_CMD28
3B AH8 DDR3 DM0 DDR4 LDM-N0 QDRIV DINVA0 MEM_DMA0
3B AJ8 DDR3 DQ6 DDR4 DQ6 QDRIV DQA6 MEM_DQA6
3B AH9 DDR3 DQ2 DDR4 DQ2 QDRIV DQA2 MEM_DQA2
3B AJ9 DDR3 DQ1 DDR4 DQ1 QDRIV DQA1 MEM_DQA1
3B AF12 DDR3 DQ3 DDR4 DQ3 QDRIV DQA3 MEM_DQA3
3B AG12 DDR3 DQ0 DDR4 DQ0 QDRIV DQA0 MEM_DQA0
3B AG10 DDR3 DQSn0 DDR4 DQSn0 QDRIV DQA17 MEM_DQSA_N0
3B AG9 DDR3 DQSp0 DDR4 DQSp0 QDRIV DQA16 MEM_DQSA_P0
3B AG11 DDR3 DQ5 DDR4 DQ5 QDRIV DQA5 MEM_DQA5
3B AH11 DDR3 DQ4 DDR4 DQ4 QDRIV DQA4 MEM_DQA4
3B AJ11 DDR3 DQ7 DDR4 DQ7 QDRIV QKA_N0 MEM_DQA7
3B AJ10 QDRIV QKA_P0 MEM_QKA_P0
3B AK7 DDR3 DQ13 DDR4 DQ13 RLDRAM3 DQ14 QDRIV DQA12 MEM_DQA13
3B AL7 DDR3 DQ15 DDR4 DQ15 RLDRAM3 DQ16 QDRIV DQA14 MEM_DQA15
3B AM6 DDR3 DM1 DDR4 UDM_n0 QDRIV QVLDA0 MEM_DMA1
3B AN6 DDR3 DQ12 DDR4 DQ12 RLDRAM3 DQ13 QDRIV DQA11 MEM_DQA12
3B AK8 DDR3 DQ8 DDR4 DQ8 RLDRAM3 DQ9 QDRIV DQA8 MEM_DQA8
3B AL8 DDR3 DQ9 DDR4 DQ9 RLDRAM3 DQ10 QDRIV DQA9 MEM_DQA9
3B AM7 DDR3 DQS_n1 DDR4 DQSU_n0 RLDRAM3 QK1n DKAn0 MEM_DQSA_N1
3B AN7 DDR3 DQS_p1 DDR4 DQSU_p0 RLDRAM3 QK1p DKAP0 MEM_DQSA_P1
3B AM9 DDR3 DQ14 DDR4 DQ14 RLDRAM3 DQ15 QDRIV DQA13 MEM_DQA14
3B AN8 RLDRAM3 DQ17 QDRIV DQA15 MEM_DQA32
3B AK10 DDR3 DQ10 DDR4 DQ10 RLDRAM3 DQ11 QDRIV DQA9 MEM_DQA32
3B AL9 DDR3 DQ11 DDR4 DQ11 RLDRAM3 DQ12 QDRIV DQA110 MEM_DQA11
3B AM5 DDR3 DM2 DDR4 LDM_n1 RLDRAM3 DQ13 QDRIV DINVA1 MEM_DMA2
3B AN4 DDR3 DQ20 DDR4 DQ20 QDRIV DQA22 MEM_DQA20
3B AP3 DDR3 DQ19 DDR4 DQ19 RLDRAM3 QVLD1 QDRIV DQA21 MEM_DQA19
3B AR3 DDR3 DQ16 DDR4 DQ16 QDRIV DQA18 MEM_DQA16
3B AP5 DDR3 DQ22 DDR4 DQ22 QDRIV DQA24 MEM_DQA22
3B AP4 DDR3 DQ18 DDR4 DQ18 QDRIV DQA20 MEM_DQA18
3B AP6 DDR3 DQSn2 DDR4 DQSLn1 RLDRAM3 DK1n QDRIV DQA35 MEM_DQSA_N2
3B AR5 DDR3 DQSp2 DDR4 DQSLp1 RLDRAM3 DK1p QDRIV DQA34 MEM_DQSA_P2
3B AU2 DDR3 DQ17 DDR4 DQ17 QDRIV DQA19 MEM_DQA17
3B AU1 DDR3 DQ21 DDR4 DQ21 QDRIV DQA23 MEM_DQA21
3B AT3 DDR3 DQ23 DDR4 DQ23 QDRIV QKA_n1 MEM_DQA23
3B AT2 QDRIV QKA_p1 MEM_QKA_P1
3B AT5 DDR3 DQ31 DDR4 DQ31 RLDRAM3 DQ34 QDRIV DQA32 MEM_DQA31
3B AT4 DDR3 DM3 DDR4 UDM_n1 QDRIV QVLDA1 MEM_DMA3
3B AR7 DDR3 DQ30 DDR4 DQ30 RLDRAM3 DQ33 QDRIV DQA31 MEM_DQA30
3B AR6 DDR3 DQ29 DDR4 DQ29 RLDRAM3 DQ32 QDRIV DQA30 MEM_DQA29
3B AU4 DDR3 DQ24 DDR4 DQ24 RLDRAM3 DQ27 QDRIV DQA25 MEM_DQA24
3B AV4 DDR3 DQ27 DDR4 DQ27 RLDRAM3 DQ30 QDRIV DQA28 MEM_DQA27
3B AV6 DDR3 DQS3n DDR4 DQSU_n1 RLDRAM3 QK3n QDRIV DKA_n1 MEM_DQSA_N3
3B AW6 DDR3 DQS3p DDR4 DQSU_p1 RLDRAM3 QK3n QDRIV DKA_p1 MEM_DQSA_P3
3B AU6 RLDRAM3 DQ35 QDRIV DQA33 MEM_DQA33
3B AU5 DDR3 DQ26 DDR4 DQ26 RLDRAM3 DQ29 QDRIV DQA27 MEM_DQA26
3B AW5 DDR3 DQ25 DDR4 DQ25 RLDRAM3 DQ28 QDRIV DQA26 MEM_DQA25
3B AW4 DDR3 DQ28 DDR4 DQ28 RLDRAM3 DQ31 QDRIV DQA29 MEM_DQA28
Level Two Title