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5.9.1. PCI Express
5.9.2. 10/100/1000 Ethernet (HPS)
5.9.3. 10/100/1000 Ethernet (FPGA)
5.9.4. FMC
5.9.5. HPS Shared I/O
5.9.6. USB 2.0 Port (HPS)
5.9.7. RS-232 UART (HPS)
5.9.8. Real-Time Clock (HPS)
5.9.9. SFP+
5.9.10. I2C Interface
5.9.11. FPGA General I/O Configuration
5.9.12. HPS SPIO Interface
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5.6.5. Logic Reset Push Button
The logic reset push button (S10) is an input to the MAX V CPLD 5M2210 System Controller. This push button is the default reset for the CPLD logic and FPGA.