Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.9.11.3. FPGA Resistor MUX

The JESD204B frame sources can be selected by resistor MUXs.

Table 44.  JESD204B Frame Source Selection

JESD204B mode Master (clock source from Clock Cleaner) Select 1 (default)

FMCA Slot Resistor MUX FMCB Slot Resistor MUX FPGA Resistor MUX
R612 R361 R575
R613 R365 R576
R621 R373 R584
R633 R383 R585

JESD204B mode Master (clock source from FPGA) Select 2

FMCA Slot Resistor MUX FMCB Slot Resistor MUX
R610 R360
R611 R361
R620 R372
R632 R382

FBHA_P/N6, FBHA_PN17, FBHA_PN21 and FBHA_PN23 are selected as transceiver channels by default.

Table 45.  FBHA6, FBHA17, FBHA21, and FBHA23 Passive MUX
MUX ID Select 1 (default) Select 2
FBHA6 MUX FBD12C2MP/N FBHA_P/N6
C367 R437
C376 R445
FBHA17 MUX FBD15C2MP/N FBHA_P/N17
C422 R470
C423 R471
FBHA21 MUX FBD15M2CP/N FBHA_P/N21
C335 R404
C336 R405
FBHA23 MUX FBD10C2MP/N FBHA_P/N23
C346 R411
C354 R427

FPGA 3A, 3E, 3G and 3H bank reference clocks can be selected from different clock sources.

Table 46.  3A, 3E, 3G and 3H Bank Reference Clock Selection
MUX ID Select 1 (default) Select 2 Select 3
REFLCK_3AMux CLK_3A FBCLK1M2C
R354 R355
R347 R348
REFClk_3EMUX LMK_CLEAN_CLK FACLK1M2C CLK_3E
R576 R577 R579
R575 R574 R578
Refsys_3EMUX LMK_SYSREF FACLK3BDIR
R585 R587
R584 R586
REFCLK_3GMUX RCLOCK_OUT FACLK2BIDIR
R602 R604
R601 R603
FA_EMI_3HMUX FACLK0M2C CLK_FAEMI
R596 R594
R595 R593

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