Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.9.7. RS-232 UART (HPS)

The development board supports two UART interfaces, the HPS debug UART and the FPGA debug UART interface. The HPS debug UART is connected to a mini-USB connector (J10) using a FT232RQ-REEL USB-to-UART bridge. The maximum supported rate for this interface is 1 Mbps. The FPGA debug UART is connected to the DB9 connector (J25) using a MAX3221 UART PHY. Board reference D11 and D12 are the HPS debug UART LEDs that illuminate to indicate TX and RX activity.

Table 39.  UART FPGA Signal Names and Functions
FPGA Pin Assignment Shared I/O Bit Schematic Signal Name Description
J18 GPIO1_IO6 UARTA_TX HPS debug UART port 1 TX
J19 GPIO1_IO7 UARTA_RX HPS debug UART PORT 1 RX
AV22 - CVP_CONFDONE HPS UART0 TX after FPGA configuration
AU21 - CRCERROR HPS UART0 RX after FPGA configuration

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