Intel® Arria® 10 SoC Development Kit User Guide

ID 683227
Date 7/12/2023
Document Table of Contents
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5.4.2. FPGA and I/O MUX CPLD Programming over On-Board USB-Blaster II

Table 20.  SW3 Configuration for On-Board USB-Blaster II Mode
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

This configuration method implements a micro-USB connector (J22), a USB 2.0 PHY device (U18), and an Altera MAX II CPLD EPM1270M256C4N (U17) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus Prime software.

The on-board USB-Blaster II in the MAX II CPLD EPM1270M256C4N normally masters the JTAG chain. The on-board USB-Blaster II shares the pins with the external header and is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J24). In addition to the JTAG interface, the on-board USB Blaster II has trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the on-board USB-Blaster II connection pins through the FPGA.

Figure 23. JTAG Chain
Note: If an external USB-Blaster (I/II) cable is plugged into the EXTERNAL JTAG HEADER, the MAX II automatically uses it as the master despite any DIP switch setting.

The MAX II CPLD (EPM1270M256C4N) is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and driving JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface is routed to a small surface-mount header only intended for debugging of first article prototypes.