Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 7/12/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Quartus Prime Design Software 2.3. Installing the Altera SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the USB-Blaster Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Quartus Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Arria 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board USB-Blaster II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External USB-Blaster
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCI Express 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
A. Additional Information
Give Feedback

1.2. Board Component Blocks

The development board features the following major component blocks:

  • Arria 10 Soc (10AS066N3F40E2SG) in a 1517-pin FBGA (FineLine Ball-Grid Array) package
  • FPGA configuration circuitry
    • Active Serial (AS) x1 or x4 configuration (EPCQ1024L)
    • MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the system controller
    • MAX V CPLD (5M2210ZF256) in a 256-pin FBGA package as the I/O multiplier CPLD
  • Clocking circuitry
    • SI5338 programmable oscillator
    • LMK04828 clock cleaner
    • HPS clock options: 25 MHz, 33 MHz, and SMA input (2V5 LVCMOS)
    • SI5112 100MHz clock generator for PCIe interface
    • SI516 148.5 MHz voltage control oscillator for SDI interface
  • Supported Memory
    • HPS memory size (HILO card):
      • 2GB DDR3 (256Mb x 40 x dual rank)
      • 1GB DDR3 (256Mb x 40 x single rank)
      • 1GB DDR4 (256Mb x 40 x single rank) - ships with kit
    • FPGA memory size (HILO Card):
      • 4GB DDR3 (256Mb x72 x dual rank)
      • 2GB DDR3 (256Mb x72 x single rank)
      • 2GB DDR4 (256Mb x 72 x single rank) - ships with kit
      • 16MB QDRV (4Mb x 36)
      • 128MB RLDRAM3(16Mb x 72)
    • HPS Boot Flash (Flash card):
      • NAND flash (x8) : 128MB (MT29F1G08ABBEAH4) - ships with kit
      • QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT) - ships with kit
      • SD Micro flash card: 4GB (Kingston) - ships with kit
    • Optional FPGA File Flash (Flash card):
      • NAND flash (x8): 128MB (MT29F1G08ABBEAH4)
      • QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT)
      • SD Micro flash card: 4GB (Kingston)
  • Communication ports
    • HPS Communication ports:
      • USB 2.0 port (PHY PN: USB3320C-EZK)
      • RGMII 10/100/1000 Ethernet port (PHY PN: KSZ9031RNXCA)
      • USB-UART port (FT232R)
      • DB-9 RS-232 Port (MAX3221)
      • I2C port (I2C1 of shared I/O bit 12 and 13)
    • FPGA I/O connections:
      • FPGA V57.1 High Pin Count FMC slot
      • FPGA Altera Low Pin Count FMC slot
      • FMC_PCIe Gen2 x8 EP cable
      • FPGA PCIe GEN1/2/3 x8 RC slot
    • FPGA Communication ports:
      • 2x SGMII Gigabit Ethernet ports (PHY PN: 88E1111-B2-NDC2C000)
      • 2x 10Gb/s SFP+ ports
      • Display port (DP)
      • SDI/SDO video port
      • SPI port
      • UART port
    • FPGA Debug ports:
      • 16-bit Trace port (FPGA Trace)
  • General user I/O
    • LEDs and displays
      • 4x FPGA user LEDs
      • 4x HPS user LEDs
      • Configuration load LED
      • Configuration done LED
      • Error LED
      • 3x Configuration select LEDs
      • 4x On-board USB-Blaster II status LEDs
      • 2x FMC interface LEDs
      • 2x UART data transmit and receive LEDs
      • Power on LED
      • Two-line character LCD display
    • Push buttons
      • CPU cold reset push button and one CPU warm reset push button
      • Logic reset push button
      • Program select push button
      • Program configuration push button
      • 4x FPGA user push buttons
      • 4x HPS user push buttons
      • External interrupt push button
    • DIP Switches
      • JTAG chain control DIP switch
      • Board settings DIP switch
      • FPGA configuration mode DIP switch
      • General user DIP switch
    • Power supply
      • 12V DC Input
    • Mechanical
      • 7.175" x 9.3" rectangular form factor
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