Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
Document Table of Contents

1.2. Board Component Blocks

The development board features the following major component blocks:

  • Arria 10 Soc (10AS066N3F40E2SG) in a 1517-pin FBGA (FineLine Ball-Grid Array) package
  • FPGA configuration circuitry
    • Active Serial (AS) x1 or x4 configuration (EPCQ1024L)
    • MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the system controller
    • MAX V CPLD (5M2210ZF256) in a 256-pin FBGA package as the I/O multiplier CPLD
  • Clocking circuitry
    • SI5338 programmable oscillator
    • LMK04828 clock cleaner
    • HPS clock options: 25 MHz, 33 MHz, and SMA input (2V5 LVCMOS)
    • SI5112 100MHz clock generator for PCIe interface
    • SI516 148.5 MHz voltage control oscillator for SDI interface
  • Supported Memory
    • HPS memory size (HILO card):
      • 2GB DDR3 (256Mb x 40 x dual rank)
      • 1GB DDR3 (256Mb x 40 x single rank)
      • 1GB DDR4 (256Mb x 40 x single rank) - ships with kit
    • FPGA memory size (HILO Card):
      • 4GB DDR3 (256Mb x72 x dual rank)
      • 2GB DDR3 (256Mb x72 x single rank)
      • 2GB DDR4 (256Mb x 72 x single rank) - ships with kit
      • 16MB QDRV (4Mb x 36)
      • 128MB RLDRAM3(16Mb x 72)
    • HPS Boot Flash (Flash card):
      • NAND flash (x8) : 128MB (MT29F1G08ABBEAH4) - ships with kit
      • QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT) - ships with kit
      • SD Micro flash card: 4GB (Kingston) - ships with kit
    • Optional FPGA File Flash (Flash card):
      • NAND flash (x8): 128MB (MT29F1G08ABBEAH4)
      • QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT)
      • SD Micro flash card: 4GB (Kingston)
  • Communication ports
    • HPS Communication ports:
      • USB 2.0 port (PHY PN: USB3320C-EZK)
      • RGMII 10/100/1000 Ethernet port (PHY PN: KSZ9031RNXCA)
      • USB-UART port (FT232R)
      • DB-9 RS-232 Port (MAX3221)
      • I2C port (I2C1 of shared I/O bit 12 and 13)
    • FPGA I/O connections:
      • FPGA V57.1 High Pin Count FMC slot
      • FPGA Altera Low Pin Count FMC slot
      • FMC_PCIe Gen2 x8 EP cable
      • FPGA PCIe GEN1/2/3 x8 RC slot
    • FPGA Communication ports:
      • 2x SGMII Gigabit Ethernet ports (PHY PN: 88E1111-B2-NDC2C000)
      • 2x 10Gb/s SFP+ ports
      • Display port (DP)
      • SDI/SDO video port
      • SPI port
      • UART port
    • FPGA Debug ports:
      • 16-bit Trace port (FPGA Trace)
  • General user I/O
    • LEDs and displays
      • 4x FPGA user LEDs
      • 4x HPS user LEDs
      • Configuration load LED
      • Configuration done LED
      • Error LED
      • 3x Configuration select LEDs
      • 4x On-board USB-Blaster II status LEDs
      • 2x FMC interface LEDs
      • 2x UART data transmit and receive LEDs
      • Power on LED
      • Two-line character LCD display
    • Push buttons
      • CPU cold reset push button and one CPU warm reset push button
      • Logic reset push button
      • Program select push button
      • Program configuration push button
      • 4x FPGA user push buttons
      • 4x HPS user push buttons
      • External interrupt push button
    • DIP Switches
      • JTAG chain control DIP switch
      • Board settings DIP switch
      • FPGA configuration mode DIP switch
      • General user DIP switch
    • Power supply
      • 12V DC Input
    • Mechanical
      • 7.175" x 9.3" rectangular form factor

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