Arria 10 SoC Development Kit User Guide

ID 683227
Date 8/09/2018
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5.3. MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210ZF256 System Controller, an Altera MAX V CPLD, for the following purposes:

  • Power sequencer
  • System reset controller
  • PCIe, FMC slot power sequencer
  • FPGA PS configuration controller
  • I2C Master controller
  • UART Level shifter
  • HPS SPI I/O expander
  • HPS Shared I/O
Table 17.  MAX V CPLD System Controller Device Pin Out
I/O Bank Board Reference Pin Name Pin Type I/O Standard Description
3 E14 P0V9Pgood Schmitt trigger input 3.3 V Power good signal of 0.9 V power rail (Active high)
3 C14 HPS_Pgood Schmitt trigger input 3.3 V HPS core voltage power good signal
3 C15 PN0V95pgood Schmitt trigger input 3.3 V 0.95 V Power supply power good signal (Active high)
3 E13 1V0_Pgood Schmitt trigger input 3.3 V 1V0 Power supply power good signal (Active high)
3 E12 1V8_Pgood Schmitt trigger input 3.3 V 1V8 Power supply power good signal (Active high)
3 D15 2V5_Pgood Schmitt trigger input 3.3 V 2V5 Power supply power good signal (Active high)
3 F14 3V3_Pgood Schmitt trigger input 3.3 V 3V3 Power supply power good signal (Active high)
3 D16 PGM_LED2 OC 3.3 V FPGA status LED.
3 F13 5V0_Pgood Schmitt trigger input 3.3 V 5V0 Power supply power good signal (Active high)
3 E15 HILOHPS_VDDPGood Schmitt trigger input 3.3 V HPS_HILO Power supply power good signal
3 E16 HILO_VDDPGood Schmitt trigger input 3.3 V HILO VDD power supply power good signal
3 F15 HILO_VDDQPGood Schmitt trigger input 3.3 V HILO VDDQ power supply power good signal
3 G14 FMCAVADJPGood Schmitt trigger input 3.3 V FMC VADJ Power supply power good signal
3 F16 FMCBVADJPGood Schmitt trigger input 3.3 V FMC VADJ Power supply power good signal
3 G13 10V_Fail_n Schmitt trigger input 3.3 V A10_12V input below 10.11 V (Active low)
3 G15 10V_good Schmitt trigger input 3.3 V A10_12V input above 10.62 V (Active low)
3 G12 LTFAUL0 Input/Output 3.3 V LT2977 Fault signal
3 G16 LTPWRGD Input/Output 3.3 V LT2977 Power good input
3 H14 FAC2MPgood Output 3.3 V 30 ms delay after FMCA_EN and FMCA_AUXEN is enabled.
3 H15 FBC2MPgood Output 3.3 V 30 ms delay after FMCB_EN and FMCB_AUXEN is enabled.
3 H13 FAM2CPgood Schmitt trigger input 3.3 V This flag indicates the power from FMC DC card is good when MAX V I/O CPLD BANK3 power uses FMC POWER.
3 H16 TSENSE_ALERTn Schmitt trigger input 3.3 V SMBUS Alert Bit when I2C hangs
3 J13 OVERTEMPn Schmitt trigger input 3.3 V Temperature is above threshold
3 J16 FAN_EN Output 3.3 V FAN Enable (Active high)
3 J12 MAXV_USB_CLK Clock input 3.3 V Clock input from USB-blaster
3 H12 NC -   -
3 J14 NC -   -
3 J15 A10_EN Output 3.3 V Arria 10 12 V input enable (Active high)
3 K16 A10_0V9_EN Output 3.3 V 0.9 V Power supply enable (Active high)
3 K13 A10_0V95_EN Output 3.3 V 0.95 V Power supply enable (Active high)
3 K15 A10_1V0_EN Output 3.3 V 1.0 V Power supply enable (Active high)
3 K14 A10_1V8_EN Output 3.3 V 1.8 V Power supply enable (Active high)
3 L16 IO_EN Output 3.3 V Arria 10 I/O power enable (Active high)
3 L11 PCIE_Auxen Output 3.3 V PCIE Aux power enable (Active high)
3 L15 PCIE_EN Output 3.3 V PCIE 3V3 enable (Active high)
3 L12 FMCA_AUXEN Output 3.3 V FMCA Aux power enable (Active high)
3 M16 FMCA_EN Output 3.3 V FMCA3V3 enable (Active high)
3 L13 FMCB_AUXEN Output 3.3 V FMCB Aux Power enable (Active high)
3 M15 FMCB_EN Output 3.3 V FMCB3V3 enable (Active high)
3 L14 Pmbus_Altertn Schmitt trigger input 3.3 V Pmbus Alert Bit input when I2C hangs.
3 N16 IO3V3_Discharge Output 3.3 V 6A discharge load for IO3V3 (Active high)
3 M13 PLL1V8_discharge Output 3.3 V 3A discharge load for IO3V3 (Active high)
3 N15 NC    
3 N14 LTCNTRL0 Output 3.3 V LT2977 Control 0
3 P15 LTCNTRL1 Output 3.3 V LT2977 Control 1
3 P14 LTWDI_RESETN Output 3.3 V LT2977 reset
3 D13 FAPRSNT_n Schmitt trigger input 3.3 V Detects signal of FMCA DC card
3 D14 FBPRSNT_N Schmitt trigger input 3.3 V Detects signal of FMCB DC card
3 F11 USB_Vflagn Schmitt trigger input 3.3 V Overcurrent flag of EXT USB power
3 F12 NC -   -
3 K12 NC -   -
3 M14 NC -   -
3 N13 NC -   -
4 R1 A10_2L_SDA Input/OC 3.3 V I2C data line.
4 P4 A10_2L_SCL OC 3.3 V I2C clock line.
4 T2 A10I2CEN Output 3.3 V Enable Arria 10 HPS I2C. (Active high)
4 P5 A10PMBUSEN Output 3.3 V Enable Arria 10 FPGA I2C. (Active high)
4 R3 A10_PMBUSDIS_N Output 3.3 V Disables Arria 10 FPGA PMBus access. (Active low)
4 N5 UARTA_RX Input 3.3 V HPS UART RX input from USB-UART.
4 P6 UARTA_TX Output 3.3 V HPS UART TX output to USB-UART.
4 N6 PCIE_PRSNT2n Input 3.3 V Detects signal from PCIe DC card.
4 R5 SFPA_LOS Input 3.3 V SFP+ A socket loss signal. (Active low)
4 M6 SFPA_TXFAULT Input 3.3 V SFP+ A socket TX fault signal. (Active low)
4 T5 SFPGA_TXDISABLE Output 3.3 V SFP+ A socket TX disable signal. (Active low)
4 P7 SFPA_RATESEL0 Output 3.3 V SFP+ A RX signaling rate selection, 0<4.25 GBd, 1 > 4.25 GBd
4 R6 SFPA_RATESEL1 Output 3.3 V SFP +A TX signaling rate selection, 0<4.25 GBd, 1 > 4.25 GBd
4 N7 SFPB_TXDISABLE Output 3.3 V SFP+ B socket TX disable signal. Active low
4 M7 SFPB_RATESEL0 Output 3.3 V SFP+ B RX signaling rate selection, 0<4.25 GBd, 1 > 4.25 GBd
4 R7 SFPB_RATESEL1 Output 3.3 V SFP +B TX signaling rate selection, 0<4.25 GBd, 1 > 4.25 GBd
4 P8 SFPB_LOS Input 3.3 V SFP+ A socket loss signal (Active low)
4 T7 SFPB_TXFAULT Input 3.3 V SFP+ A socket tx fault signal (Active low)
4 N8 SFPA_MOD0_PRSNTn Input 3.3 V Detect signal of SFP+ module in slot A (Active low)
4 R8 SFPB_MOD0_PRSNTn Input 3.3 V Detect signal of SFP+ module in Slot B. (Active low)
4 T8 NC - 3.3 V -
4 T9 NC - 3.3 V -
4 R9 Eneta_HPS_Intn Input 3.3 V Interrupt input from Ethernet port 3
4 M9 Logic_resetn Input 3.3 V FPGA_logic reset input
4 M8 EXT_intn Input 3.3 V HPS External interrupt
4 M10 UART1_RX Input 3.3 V DB9 RS232 UART RX
4 R10 UART1_TX Output 3.3 V DB9 RS232 UART TX
4 N10 NC Output 3.3 V -
4 T11 LMK_reset Output 3.3 V LMK Clock cleaner reset (Active high)
4 P10 NC - 3.3 V -
4 R11 NC - 3.3 V -
4 T12 ENET_HPS_RESETn Output 3.3 V Ethernet port 3 reset (Active low)
4 N11 USB_RESET Output 3.3 V USB PHY reset (Active high)
4 T13 PCIE_PERSTn Output 3.3 V This signal needs to be held low if PCIE_auxEn and PCIE_EN are not active. 15 ms delay to set this high after PCIE_EN is active. PCIe RC slot reset, active low.
4 R13 RESET_HPS_UARTA_N Output 3.3 V UART_RESET (Active low)
4 R12 MAX2toMAXV0 Input/Output 3.3 V Interbus between MAX II and MAX V
4 P11 MAX2toMAXV1 Input/Output 3.3 V Interbus between MAX II and MAX V
4 N12 MAX2toMAXV2 Input/Output 3.3 V Interbus between MAX II and MAX V
4 R14 MAX2toMAXV3 Input/Output 3.3 V Interbus between MAX II and MAX V
4 P12 MAX2toMAXV4 Input/Output 3.3 V Interbusbetween MAX II and MAX V
4 T15 MAX2toMAXV5 Input/Output 3.3 V Interbus between MAX II and MAX V
4 R16 MAX2toMAXV6 Input/Output 3.3 V Interbus between MAX II and MAX V
4 P13 MAX2toMAXV7 Input/Output 3.3 V Interbus between MAX II and MAX V
4 M11 MAX2toMAXV8 Input/Output 3.3 V Interbus between MAX II and MAX V
4 M12 MAX2toMAXV9 Input/Output 3.3 V Interbus between MAX II and MAX V
4 N9 MAX2toMAXV10 Input/Output 3.3 V Interbus between MAX II and MAX V
4 R4 MAX2toMAXV11 Input/Output 3.3 V Interbus between MAX II and MAX V
4 T10 MAX2toMAXV12 Input/Output 3.3 V Interbus between MAX II and MAX V
4 T4 MAX2toMAXV13 Input/Output 3.3 V Interbus between MAX II and MAX V
2 D4 USER_LED_FPGA0 OC 2.5 V USER FPGA LED 0 output
2 B1 USER_LED_FPGA1 OC 2.5 V USER FPGA LED 1 output
2 C5 USER_LED_FPGA2 OC 2.5 V USER FPGA LED 2 output
2 C4 USER_LED_FPGA3 OC 2.5 V USER FPGA LED 3 output
2 B4 USER_LED_HPS0 OC 2.5 V HPS LED 0 output
2 D6 USER_LED_HPS1 OC 2.5 V HPS LED 1 output
2 E6 USER_LED_HPS2 OC 2.5 V HPS LED 2 output
2 B5 USER_LED_HPS3 OC 2.5 V HPS LED 3 output
2 A5 MAX_ERROR OC 2.5 V Board abnormal indicator
2 D7 MAX_LOAD OC 2.5 V FPGA status LED
2 B6 MAX_CONF_DONE OC 2.5 V FPGA status LED
2 E7 File_Presentn Input 2.5 V File flash present flag
2 C8 FACTORY_LOAD OC 2.5 V FPGA status LED
2 B7 PGM_LED0 OC 2.5 V FPGA status LED
2 D8 PGM_SEL Input 2.5 V FPGA external trigger
2 A7 BF_Presentn Input 2.5 V Boot Flash present flag
2 B8 USER_DIPSW_HPS0 Input 2.5 V User DIP HPS 0
2 A8 USER_DIPSW_HPS1 Input 2.5 V User DIP HPS 1
2 A9 USER_DIPSW_HPS2 Input 2.5 V User DIP HPS 2
2 E9 USER_DIPSW_HPS3 Input 2.5 V User DIP HPS 3
2 B9 USER_DIPSW_FPGA0 Input 2.5 V User DIP FPGA 0
2 D9 USER_DIPSW_FPGA1 Input 2.5 V User DIP FPGA 1
2 A10 USER_DIPSW_FPGA2 Input 2.5 V User DIP FPGA 2
2 C9 USER_DIPSW_FPGA3 Input 2.5 V User DIP FPGA 3
2 E10 HPS_WARM_RESET1N Input 2.5 V Trace reset from MAX II (Active low)
2 A11 HPS_WAM_RESETn Input 2.5 V Warm reset Pushbutton (Active low)
2 B11 HPS_cold_resetn Input 2.5 V COLD reset Pushbuttion (Active low)
2 A12 DC_Power_CTRL Input 2.5 V DC card power on/off switch.

0 turn off DC power

1 turn on DC power

2 E11 I2C_flag Input 2.5 V I2C master selection, '0' MAX V, '1' HPS
2 B12 PGM_CONFIG Input 2.5 V FPGA external trigger
2 C11 Security_mode Input 2.5 V FPGA mode bit
2 B13 PGM_LED1 OC 2.5 V FPGA status LED
2 D12 MAXVtoMAXV4 Input/Output 2.5 V Interbus between MAX Vs
2 B14 MAXVtoMAXV5 Input/Output 2.5 V Interbus between MAX Vs
2 C13 MAXVtoMAXV6 Input/Output 2.5 V Interbus between MAX Vs
2 B16 MAXVtoMAXV7 Input/Output 2.5 V Interbus between MAX Vs
2 A13 MAXVtoMAXV8 Input/Output 2.5 V Interbus between MAX Vs
2 A15 MAXVtoMAXV9 Input/Output 2.5 V Interbus between MAX Vs
2 A2 USER_PB_HPS0 Input 2.5 V HPS user push button 0
2 A4 USER_PB_HPS1 Input 2.5 V HPS user push button 1
2 A6 USER_PB_HPS2 Input 2.5 V HPS user push button 2
2 B10 USER_PB_HPS3 Input 2.5 V HPS user push button 3
2 B3 USER_PB_FPGA0 Input 2.5 V FPGA user push button 0
2 C10 USER_PB_FPGA1 Input 2.5 V FPGA user push button 1
2 C12 USER_PB_FPGA2 Input 2.5 V FPGA user push button 2
2 C6 USER_PB_FPGA3 Input 2.5 V FPGA user push button 3
2 C7 MAXVtoMAXV3 Input/Output 2.5 V Interbus between MAX Vs
2 D10 MAXVtoMAXV10 Input/Output 2.5 V Interbus between MAX Vs
2 D11 MAXVtoMAXV11 Input/Output 2.5 V Interbus between MAX Vs
2 D5 MAXVtoMAXV12 Input/Output 2.5 V Interbus between MAX Vs
2 E8 MAXVtoMAXV13 Input/Output 2.5 V Interbus between MAX Vs
1 D3 MSEL0 Input 1.8 V FPGA program mode selection
1 C2 MSEL1 Input 1.8 V FPGA program mode selection
1 C3 MSEL2 Input 1.8 V FPGA program mode selection
1 E3 MFD0 Input/Output 1.8 V EPCQ data0
1 D2 MFD1 Input/Output 1.8 V EPCQ data1
1 E4 MFD2 Input/Output 1.8 V EPCQ data2
1 D1 MFD3 Input/Output 1.8 V EPCQ data3
1 E5 CLK_50M_MAX Output 1.8 V 50 MHz clock to FPGA
1 F3 MFCSN Output 1.8 V EPCQ chip select.
1 E1 MFCLK Output 1.8 V EPCQ chip clock.
1 F4 HPSUARTA_TX Input 1.8 V HPS UART TX.
1 F2 HPSUARTA_RX Output 1.8 V HPS UART RX.
1 F1 SPIM1_MOSI Input 1.8 V SPI data input.
1 F6 SPIM1_SS0_N Input 1.8 V SPI chip select 0
1 G2 SPIM1_SS1_N Input 1.8 V SPI chip select 1
1 G3 SPIM1_MISO Output 1.8 V SPI data output.
1 G1 MAXVtoMAXV0 Input/Output 1.8 V Interbus between MAX Vs
1 G4 MAXVtoMAXV1 Input/Output 1.8 V Interbus between MAX Vs
1 H2 MAXVtoMAXV2 Input/Output 1.8 V Interbus between MAX Vs
1 G5 MAX_IO_CLK Output 1.8 V 50Mhz Clock Output to IO MAXV CPLD
1 H3 A10SH_GPIO0 Input/Output 1.8 V HPS GPIO 5
1 J1 A10SH_GPIO1 Input/Output 1.8 V HPS GPIO 13
1 H4 A10SH_GPIO2 Input/Output 1.8 V HPS GPIO 16
1 J2 A10SH_GPIO3 Input/Output 1.8 V HPS GPIO 17
1 H5 CLK_50M_MAX Input 1.8 V MAX V 50 MHz reference clock
1 J5 SPIM1_CLK Input 1.8 V SPIM1_CLK input
1 J4 PS_D0 Output 1.8 V Passive configure D0
1 K1 Nconfig Output 1.8 V Passive configure Nconfig output
1 J3 DCLK Output 1.8 V Program Clock
1 K2 CVP_configDone Input 1.8 V CVP configure done input during configuration, UART_TX after configuration
1 K5 NSTATUS Input 1.8 V Status bit during FPGA configuration
1 L1 conf_done Input 1.8 V Configuration done
1 L2 DEV_CLRN Output 1.8 FPGA reset bit
1 K3 CRCerror Output 1.8 V CRCerror during configuration, UART_RX after configuration
1 M1 Dedicated_TX Input 1.8 V Dedicated UART TX input
1 M2 Daticated_RX Output 1.8 V Dedicated UART RX Output
1 L4 FPGA_IO5 Input 1.8 V FPGA_IO5
1 L3 FPGA_IO4 Output 1.8 V FPGA_IO4
1 N1 FPGA_IO3 Output 1.8 V FPGA_IO3
1 M4 FPGA_IO2 Output 1.8 V FPGA_IO2
1 N2 FPGA_IO1 Input/Output 1.8 V FPGA_IO1
1 M3 FPGA_IO0 Input/Output 1.8 V FPGA_IO0
1 N3 PCIE1V8_PERSTn Output 1.8 V 15 ms delay PCIE-PHY 0_Reset after PCIE_En is activated if I/O MAX V function is disabled.
1 P2 PCIE1V8_PERST1n Output 1.8 V PCIE_PHY1 reset must be connected to the I/O MAX V bit R16 (FBLAP33) via interbus if the I/O MAX V function is disabled.
1 E2 BQSPI_RESETN Input/Output 1.8 V Boot flash reset
1 F5 HPS_NPOR Output 1.8 V NPOR output of HPS
1 H1 HPS_NRST Output 1.8 V NRST output of HPS
1 K4 FILE_RESETN Output 1.8 V File flash reset
1 L5 Dedicated_OE Input 1.8 V Dedicated UART Enable input
1 P3 M5_JTAG_TCK Input 1.8 V JTAG clock
1 L6 M5_JTAG_TDI Input 1.8 V JTAG data in
1 M5 M5_JTAG_TDO Output 1.8 V JTAG data out
1 N4 M5_JTAG_TMS Input 1.8 V JTAG_TMS

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