5.9.1. PCI Express 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
4.4.12. The Clock Control
The Clock Control application sets the three programmable oscillators to any frequency between 10 MHz and 810 MHz. The frequencies support eight digits of precision to the right of the decimal point.
The Clock Control communicates with the MAX V device on the board through the JTAG bus. The programmable oscillators are connected to the MAX V device through a 2-wire serial bus.
Figure 21. Clock Controller Window
Each Si5338 tab displays the same GUI controls for each clock generators. Each tab allows for separate control. The Si5338 is capable of synthesizing four independent user-programmable clock frequencies up to 350 MHz and select frequencies up to 710 MHz.
|F_vco||Displays the generating signal value of the voltage-controlled oscillator.|
|Registers||Display the current frequencies for each oscillator.|
|Frequency (MHz)||Allows you to specify the frequency of the clock.|
|Disable all||Disable all oscillators at once.|
|Read||Reads the current frequency setting for the oscillator associated with the active tab.|
|Default||Sets the frequency for the oscillator associated with the active tab back to its default value. The default is restored by power cycling the board.|
|Set||Sets the programmable oscillator frequency for the selected clock to the value in the CLK0 to CLK3 controls for each Si5338. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies.|
|Import||Import register map file generated from Silicon Laboratories ClockBuilder Desktop.|