Arria® 10 SX SoC Development Kit User Guide

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ID 683227
Date 11/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 SX SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Development Kit Components 6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 SX SoC Development Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC FPGA Embedded Development Suite (EDS) 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver 2.3.5. SD Card Image with Example Software
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Development Kit Components x
5.1. Board Overview 5.2. Featured Device: Arria® 10 SX SoC 5.3. MAX® V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over Onboard Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. Onboard Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe* 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughter Cards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 SX SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Development Kit Components
6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide
A. Safety and Regulatory Compliance Information

5.9.4. FMC

The FMCA slot is compliant with the V57.1 spec. All FMC V57.1 1.8 V daughter cards can be plugged into the FMCA slot. The FMCB slot is designed based on the Altera 16-transceiver FMCB specification.

Note: Check the signal connections if your FMC card must be put in the FMCB slot.
Table 31.  FMC Port A Transceiver Pin Assignments
FPGA Pin Assignment Schematic Signal Name Direction Description
E36 FAD9C2MN Output FMCA Slot Channel 9 transmitter
E37 FAD9C2MP Output FMCA Slot Channel 9 transmitter
K30 FAD9M2CN Input FMCA Slot Channel 9 receiver
K31 FAD9M2CP Input FMCA Slot Channel 9 receiver
F34 FAD8C2MN Output FMCA Slot Channel 8 transmitter
F35 FAD8C2MP Output FMCA Slot Channel 8 transmitter
K34 FAD8M2CN Input FMCA Slot Channel 8 receiver
K35 FAD8M2CP Input FMCA Slot Channel 8 receiver
F38 FAD7C2MN Output FMCA Slot Channel 7 transmitter
F39 FAD7C2MP Output FMCA Slot Channel 7 transmitter
L32 FAD7M2CN Input FMCA Slot Channel 7 receiver
L33 FAD7M2CP Input FMCA Slot Channel 7 receiver
G36 FAD6C2MN Output FMCA Slot Channel 6 transmitter
G37 FAD6C2MP Output FMCA Slot Channel 6 transmitter
M30 FAD6M2CN Input FMCA Slot Channel 6 receiver
M31 FAD6M2CP Input FMCA Slot Channel 6 receiver
L29 LMK_FMCCLK_P input FMCA reference clock from Clock cleaner
L28 LMK_FMCCLK_N input FMCA reference clock from Clock cleaner
N29 FAGBTCLK0M2CP input FMCA SLOT reference Clock 0
N28 FAGBTCLK0M2CN input FMCA SLOT reference Clock 0
H38 FAD5C2MN Output FMCA Slot Channel 5 transmitter
H39 FAD5C2MP Output FMCA Slot Channel 5 transmitter
M34 FAD5M2CN Input FMCA Slot Channel 5 receiver
M35 FAD5M2CP Input FMCA Slot Channel 5 receiver
J36 FAD4C2MN Output FMCA Slot Channel 4 transmitter
J37 FAD4C2MP Output FMCA Slot Channel 4 transmitter
N32 FAD4M2CN Input FMCA Slot Channel 4 receiver
N33 FAD4M2CP Input FMCA Slot Channel 4 receiver
K38 FAD3C2MN Output FMCA Slot Channel 3 transmitter
K39 FAD3C2MP Output FMCA Slot Channel 3 transmitter
P30 FAD3M2CN Input FMCA Slot Channel 3 receiver
P31 FAD3M2CP Input FMCA Slot Channel 3 receiver
L36 FAD2C2MN Output FMCA Slot Channel 2 transmitter
L37 FAD2C2MP Output FMCA Slot Channel 2 transmitter
P34 FAD2M2CN Input FMCA Slot Channel 2 receiver
P35 FAD2M2CP Input FMCA Slot Channel 2 receiver
M38 FAD1C2MN Output FMCA Slot Channel 1 transmitter
M39 FAD1C2MP Output FMCA Slot Channel 1 transmitter
R32 FAD1M2CN Input FMCA Slot Channel 1 receiver
R33 FAD1M2CP Input FMCA Slot Channel 1 receiver
N36 FAD0C2MN Output FMCA Slot Channel 0 transmitter
N37 FAD0C2MP Output FMCA Slot Channel 0 transmitter
T30 FAD0M2CN Input FMCA Slot Channel 0 receiver
T31 FAD0M2CP Input FMCA Slot Channel 0 receiver
R29 FAGBTCLK1M2CP input FMCA SLOT reference Clock 1
R28 FAGBTCLK1M2CN input FMCA SLOT reference Clock 1
Table 32.  FMC Port B Transceiver Pin Assignments
FPGA Pin Assignment Schematic Signal Name Direction Description
U29 REFCLK1_FMCB_P input FMCB Reference Clock 1 from Clock synthesizer
U28 REFCLK1_FMCB_N input FMCB Reference Clock 1 from Clock synthesizer
P38 FBD15C2MN Output FMCB Slot Channel 15 transmitter
P39 FBD15C2MP Output FMCB Slot Channel 15 transmitter
T34 FBD15M2CN Input FMCB Slot Channel 15 receiver
T35 FBD15M2CP Input FMCB Slot Channel 15 receiver
R36 FBD14C2MN Output FMCB Slot Channel 14 transmitter
R37 FBD14C2MP Output FMCB Slot Channel 14 transmitter
U32 FBD14M2CN Input FMCB Slot Channel 14 receiver
U33 FBD14M2CP Input FMCB Slot Channel 14 receiver
T38 FBD13C2MN Output FMCB Slot Channel 13 transmitter
T39 FBD13C2MP Output FMCB Slot Channel 13 transmitter
V30 FBD13M2CN Input FMCB Slot Channel 13 receiver
V31 FBD13M2CP Input FMCB Slot Channel 13 receiver
U36 FBD12C2MN Output FMCB Slot Channel 12 transmitter
U37 FBD12C2MP Output FMCB Slot Channel 12 transmitter
V34 FBD12M2CN Input FMCB Slot Channel 12 receiver
V35 FBD12M2CP Input FMCB Slot Channel 12 receiver
V38 FBD11C2MN Output FMCB Slot Channel 11 transmitter
V39 FBD11C2MP Output FMCB Slot Channel 11 transmitter
W32 FBD11M2CN Input FMCB Slot Channel 11 receiver
W33 FBD11M2CP Input FMCB Slot Channel 11 receiver
W36 FBD10C2MN Output FMCB Slot Channel 10 transmitter
W37 FBD10C2MP Output FMCB Slot Channel 10 transmitter
Y30 FBD10M2CN Input FMCB Slot Channel 10 receiver
Y31 FBD10M2CP Input FMCB Slot Channel 10 receiver
W29 FBGBTCLK1M2CP input Reference Clock from FMCB slot channel 1
W28 FBGBTCLK1M2CN input Reference Clock from FMCB slot channel 1
AM38 FBD7C2MN Output FMCB Slot Channel 7 transmitter or PCIe* EP Channel 7 transmitter
AM39 FBD7C2MP Output FMCB Slot Channel 7 transmitter or PCIe* EP Channel 7 transmitter
AH30 FBD7M2CN Input FMCB Slot Channel 7 receiver or PCIe* EP Channel 7 receiver
AH31 FBD7M2CP Input FMCB Slot Channel 7 receiver or PCIe* EP Channel 7 receiver
AN36 FBD6C2MN Output FMCB Slot Channel 6 transmitter or PCIe* EP Channel 6 transmitter
AN37 FBD6C2MP Output FMCB Slot Channel 6 transmitter or PCIe* EP Channel 6 transmitter
AJ32 FBD6M2CN Input FMCB Slot Channel 6 receiver or PCIe* EP Channel 6 receiver
AJ33 FBD6M2CP Input FMCB Slot Channel 6 receiver or PCIe* EP Channel 6 receiver
AP38 FBD5C2MN Output FMCB Slot Channel 5 transmitter or PCIe* EP Channel 5 transmitter
AP39 FBD5C2MP Output FMCB Slot Channel 5 transmitter or PCIe* EP Channel 5 transmitter
AK34 FBD5M2CN Input FMCB Slot Channel 5 receiver or PCIe* EP Channel 5 receiver
AK35 FBD5M2CP Input FMCB Slot Channel 5 receiver or PCIe* EP Channel 5 receiver
AP34 FBD4C2MN Output FMCB Slot Channel 4 transmitter or PCIe* EP Channel 4 transmitter
AP35 FBD4C2MP Output FMCB Slot Channel 4 transmitter or PCIe* EP Channel 4 transmitter
AK30 FBD4M2CN Input FMCB Slot Channel 4 receiver or PCIe* EP Channel 4 receiver
AK31 FBD4M2CP Input FMCB Slot Channel 4 receiver or PCIe* EP Channel 4 receiver
AR36 FBD3C2MN Output FMCB Slot Channel 3 transmitter or PCIe* EP Channel 3 transmitter
AR37 FBD3C2MP Output FMCB Slot Channel 3 transmitter or PCIe* EP Channel 3 transmitter
AL32 FBD3M2CN Input FMCB Slot Channel 3 receiver or PCIe* EP Channel 3 receiver
AL33 FBD3M2CP Input FMCB Slot Channel 3 receiver or PCIe* EP Channel 3 receiver
AT38 FBD2C2MN Output FMCB Slot Channel 2 transmitter or PCIe* EP Channel 2 transmitter
AT39 FBD2C2MP Output FMCB Slot Channel 2 transmitter or PCIe* EP Channel 2 transmitter
AM34 FBD2M2CN Input FMCB Slot Channel 2 receiver or PCIe* EP Channel 2 receiver
AM35 FBD2M2CP Input FMCB Slot Channel 2 receiver or PCIe* EP Channel 2 receiver
AL29 REFCLK0_FMCB_P Input FMCB Reference Clock 0 from Clock synthesizer
AL28 REFCLK0_FMCB_N Input FMCB Reference Clock 0 from Clock synthesizer
AN29 FBGBTCLK0M2CP Input FMCB slot reference clock channel 0 or PCIe* EP reference clock
AN28 FBGBTCLK0M2CN Input FMCB slot reference clock channel 0 or PCIe* EP reference clock
AT34 FBD1C2MN Output FMCB Slot Channel 1 transmitter or PCIe* EP Channel 1 transmitter
AT35 FBD1C2MP Output FMCB Slot Channel 1 transmitter or PCIe* EP Channel 1 transmitter
AM30 FBD1M2CN Input FMCB Slot Channel 1 receiver or PCIe* EP Channel 1 receiver
AM31 FBD1M2CP Input FMCB Slot Channel 1 receiver or PCIe* EP Channel 1 receiver
AU36 FBD0C2MN Output FMCB Slot Channel 0 transmitter or PCIe* EP Channel 0 transmitter
AU37 FBD0C2MP Output FMCB Slot Channel 0 transmitter or PCIe* EP Channel 0 transmitter
AN32 FBD0M2CN Input FMCB Slot Channel 0 receiver or PCIe* EP Channel 0 receiver
AN33 FBD0M2CP Input FMCB Slot Channel 0 receiver or PCIe* EP Channel 0 receiver
AV38 FBD9C2MN Output FMCB Slot Channel 9 transmitter
AV39 FBD9C2MP Output FMCB Slot Channel 9 transmitter
AP30 FBD9M2CN Input FMCB Slot Channel 9 receiver
AP31 FBD9M2CP Input FMCB Slot Channel 9 receiver
AV34 FBD8C2MN Output FMCB Slot Channel 8 transmitter
AV35 FBD8C2MP Output FMCB Slot Channel 8 transmitter
AR32 FBD8M2CN Input FMCB Slot Channel 8 receiver
AR33 FBD2M2CP Input FMCB Slot Channel 8 receiver

The FMCA slot is designed to be compatible with the requirements of FMC V57.1. This slot can be used to support an external FMC memory card (DDR3 or DDR4).

Table 33.  FMCA LVDS Signal I/O Assignment
BANK Pin Number Schematic Signal Name DDR3 Interface (optional) DDR4 Interface (optional)
3H P15 FAHAN0 DDR3 DQ4 DDR4 DQ4
3H P14 FAHAP0 DDR3 DM0 DDR4 LDM_n0
3H N14 FAHAN1 DDR3 DQ5 DDR4 DQ5
3H M14 FAHAP1 DDR3 DQ6 DDR4 DQ6
3H J14 FAHAN2 DDR3 DQ1 DDR4 DQ1
3H J13 FAHAP2 DDR3 DQ0 DDR4 DQ0
3H L15 FAHAN3 DDR3 DQS 0n DDR4 DQSL_n0
3H L14 FAHAP3 DDR3 DQS 0p DDR4 DQSL_p0
3H L13 FAHAN4 DDR3 DQ2 DDR4 DQ2
3H L12 FAHAP4 DDR3 DQ3 DDR4 DQ3
3H K13 FAHAN5 DDR3 DQ7 DDR4 DQ7
3H K12 FAHAP5 --- ---
3H H14 FALAN0 DDR3 DQ9 DDR4 DQ9
3H G14 FALAP0 DDR3 DQ8 DDR4 DQ8
3H D14 FALAN3 DDR3 DQ11 DDR4 DQ11
3H C14 FALAP3 DDR3 DQ10 DDR4 DQ10
3H D13 FALAN2 DDR3 DQ14 DDR4 DQ14
3H C13 FALAP2 DDR3 DQ12 DDR4 DQ12
3H E13 FA_LA_DEVCLK_N DDR3 DQS1n DDR4 DQSU0n
3H E12 FA_LA_DEVCLK_P DDQ3 DQS1p DDQ4 DQSU0p
3H H13 FALAN4 DDR3 DQ13 DDQ4 DQ13
3H H12 FALAP4 240-Ohm reference resistor 240-Ohm reference resistor
3H F14 FA_LA_SYSREF_N DDR3 DQ15 DDR4 DQ15
3H F13 FA_LA_SYSREF_P DDR3 DM1 DDR4 UDM_n0
3H C12 FAHAN6 DDR3 DQ20 DDR4 DQ20
3H C11 FAHAP6 DDR3 DQ22 DDR4 DQ22
3H E11 FAHAN7 DDR3 DQ17 DDR4 DQ17
3H D11 FAHAP7 DDR3 DQ18 DDR4 DQ18
3H G12 FAHAN8 DDR3 DQ19 DDR4 DQ19
3H F12 FAHAP8 DDR3 DQ16 DDR4 DQ16
3H G10 FAHAN9 DDR3 DQSn2 DDR4 DQSL1n
3H F10 FAHAP9 DDR3 DQSp2 DDR4 DQSl1p
3H E10 FAHAN10 DDR3 DM2 DDR4 LDM_n1
3H D10 FAHAP10 DDR3 DQ21 DDR4 DQ21
3H H11 FAHAN11 DDR3DQ23 DDR4DQ23
3H G11 FAHAP11
3H B10 FALAN6 DDR3 DMA3 DDR4 UDM_n1
3H A10 FALAP6 DDR3 DQ31 DDR4 DQ31
3H B9 FALAN7 DDR3 DQ30 DDR4 DQ30
3H A9 FALAP7
3H B12 FALAN8 DDR3 DQ29 DDR4 DQ29
3H B11 FALAP8 DDR3 DQ28 DDR4 DQ28
3H A13 FALAN9 DDR3 DQSn3 DDR4 DQSU1n
3H A12 FALAP9 DDR3 DQSp3 DDR4 DQSU1p
3H A8 FALAN10 DDR3 DQ25 DDR4 DQ25
3H A7 FALAP10 DDR3 DQ26 DDR4 DQ26
3H D9 FALAN11 DDR3 DQ24 DDR4 DQ24
3H C9 FALAP11 DDR3 DQ27 DDR4 DQ27
3G F8 FAHAN12 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G E8 FAHAP12 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G C7 FAHAN13 DM of DDR3 Byte 8 DM of DDR4 Byte 8
3G B7 FAHAP13 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G D8 FAHAN14 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G C8 FAHAP14 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G C6 FAHAN15 DQS of DDR3 byte 8 DQS of DDR4 byte 8
3G B6 FAHAP15 DQS of DDR3 byte 8 DQS of DDR4 byte 8
3G B5 FAHAN16 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G A5 FAHAP16 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G B4 FAHAN17 DQ of DDR3 Byte 8 DQ of DDR4 Byte 8
3G A4 FAHAP17 No use DDR4 Alertn
3G C4 FALAN20 BA2 of DDR3 Bank Address line BG0 of DDR4 Group line
3G C3 FALAP20 BA1 of DDR3 Bank address line BA1 of DDR4 BANK address line
3G D3 FALAN21 BA0 of DDR3 BANK address line BA0 of DDR4 BANK address line
3G C2 FALAP21 CASn of DDR3 Control line A17 of DDR4 address line
3G F7 FAHAN22 RASn of DDR3 Control line A16 of DDR4 address line
3G E7 FAHAP22 A15 of DDR3 Address line A15 of DDR4 Address line
3G D5 FALAN15 A14 of DDR3 Address line A14 of DDR4 Address line
3G D4 FALAP15 A13 of DDR3 Address line A13 of DDR4 Address line
3G E6 FALAN16 A12 of DDR3 Address line A12 of DDR4 Address line
3G D6 FALAP16 240-Ohm reference resistor 240-Ohm reference resistor
3G F5 FA_EMI_CLKN 133Mhz DDR reference clock 133Mhz DDR reference clock
3G E5 FA_EMI_CLKP 133Mhz DDR reference clock 133Mhz DDR reference clock
3G H9 FAHAN19 A11 of DDR3 Address line A11 of DDR4 Address line
3G H8 FAHAP19 A10 of DDR3 Address line A10 of DDR4 Address line
3G G9 FALAN17 A9 of DDR3 Address line A9 of DDR4 Address line
3G F9 FALAP17 A8 of DDR3 Address line A8 of DDR4 Address line
3G K8 FPGA_RCLK_3Gn A7 of DDR3 Address line A7 of DDR4 Address line
3G J8 FPGA_RCLK_3Gp A6 of DDR3 Address line A6 of DDR4 Address line
3G G6 FALAN19 A5 of DDR3 Address line A5 of DDR4 Address line
3G G5 FALAP19 A4 of DDR3 Address line A4 of DDR4 Address line
3G H7 FALAN18 A3 of DDR3 Address line A3 of DDR4 Address line
3G G7 FALAP18 A2 ofDDR3 Address line A2 ofDDR4 Address line
3G J6 FAHAN23 A1 of DDR3 Address line A1 of DDR4 Address line
3G H6 FAHAP23 A0 of DDR3 Address line A0 of DDR4 Address line
3G L10 FAHAN20 No use DDR4 PAR
3G K10 FAHAP20 No use CSN1 of DDR4 control line
3G K11 FAHAN13 DDR3 interface clock DDR4 interface clock
3G J11 FAHAP13 DDR3 interface clock DDR4 interface clock
3G N13 FALAN12 DDR3 ClKe1 DDR4 CKe1
3G M12 FALAP12 DDR3 CKe0 DDR4 CKe0
3G N11 FAHAN21 DDR3 ODT1 DDR4 ODT1
3G M10 FAHAP21 DDR3 ODT0 DDR4 ODT0
3G J10 FALAN14 DDR3 CSn1 DDR4 ACTn
3G J9 FALAP14 DDR3 CSn0 DDR4 CSn0
3G N12 FAHAN18 DDR3 Resetn DDR4 Resetn
3G M11 FAHAP18 DDR3 Wen DDR4 BG1
3F G4 FALAN22 DDR3 DQ4 DDR4 DQ4
3F F4 FALAP22 DDR3 DM0 DDR4 LDM_n0
3F D1 FALAN23 DDR3 DQ5 DDR4 DQ5
3F C1 FALAP23 DDR3 DQ6 DDR4 DQ6
3F E2 FALAN24 DDR3 DQ1 DDR4 DQ1
3F E1 FALAP24 DDR3 DQ0 DDR4 DQ0
3F F3 FALAN25 DDR3 DQS 0n DDR4 DQSL_n0
3F E3 FALAP25 DDR3 DQS 0p DDR4 DQSL_p0
3F G2 FALAN26 DDR3 DQ2 DDR4 DQ2
3F F2 FALAP26 DDR3 DQ3 DDR4 DQ3
3F H2 FALAN27 DDR3 DQ7 DDR4 DQ7
3F G1 FALAP27
3F J5 FAHBN0 DDR3 DQ9 DDR4 DQ9
3F J4 FAHBP0 DDR3 DQ8 DDR4 DQ8
3F J1 FAHBN1 DDR3 DQ11 DDR4 DQ11
3F H1 FAHBP1 DDR3 DQ10 DDR4 DQ10
3F H4 FAHBN2 DDR3 DQ14 DDR4 DQ14
3F H3 FAHBP2 DDR3 DQ12 DDR4 DQ12
3F K2 FAHBN3 DDR3 DQS1n DDR4 DQSU0n
3F K1 FAHBP3 DDQ3 DQS1p DDQ4 DQSU0p
3F L3 FAHBN4 DDR3 DQ13 DDQ4 DQ13
3F L2 FAHBP4 240-Ohm reference resistor 240-Ohm reference resistor
3F K3 FAHBN5 DDR3 DQ15 DDR4 DQ15
3F J3 FAHBP5 DDR3 DM1 DDR4 UDM_n0
3F N7 FAHBN6 DDR3 DQ20 DDR4 DQ20
3F N6 FAHBP6 DDR3 DQ22 DDR4 DQ22
3F K6 FAHBN7 DDR3 DQ17 DDR4 DQ17
3F K5 FAHBP7 DDR3 DQ18 DDR4 DQ18
3F L7 FAHBN8 DDR3 DQ19 DDR4 DQ19
3F K7 FAHBP8 DDR3 DQ16 DDR4 DQ16
3F M7 FAHBN9 DDR3 DQSn2 DDR4 DQSL1n
3F M6 FAHBP9 DDR3 DQSp2 DDR4 DQSl1p
3F M4 FAHBN10 DDR3 DM2 DDR4 LDM_n1
3F L4 FAHBP10 DDR3 DQ21 DDR4 DQ21
3F M5 FALAN28 DDR3DQ23 DDR4DQ23
3F L5 FALAP28
3F P10 FALAN29 DDR3 DMA3 DDR4 UDM_n1
3F N9 FALAP29 DDR3 DQ31 DDR4 DQ31
3F M9 FAHBN13 DDR3 DQ30 DDR4 DQ30
3F N8 FAHBP13
3F R10 FALAN30 DDR3 DQ29 DDR4 DQ29
3F P9 FALAP30 DDR3 DQ28 DDR4 DQ28
3F R8 FALAN31 DDR3 DQSn3 DDR4 DQSU1n
3F P8 FALAP31 DDR3 DQSp3 DDR4 DQSU1p
3F R11 FALAN33 DDR3 DQ25 DDR4 DQ25
3F P11 FALAP33 DDR3 DQ26 DDR4 DQ26
3F L9 FALAN32 DDR3 DQ24 DDR4 DQ24
3F L8 FALAP32 DDR3 DQ27 DDR4 DQ27
Table 34.  FMCB LVDS Signal I/O Assignment
BANK Pin Number Schematic Signal Name
3E U7 FBHA_N6
3E T7 FBHA_P6
3E U6 FPGA_Refsys_3En
3E U5 FPGA_Refsys_3Ep
3E V7 FBHA_P17
3E V6 FBHA_N17
3E W6 Refclk_3En
3E W5 Refclk_3Ep
3E U4 FBLAN20
3E T4 FBLAP20
3E T3 FBLAN21
3E T2 FBLAP21
3E U2 FBLAN22
3E U1 FBLAP22
3E V2 FBLAN23
3E V1 FBLAP23
3E W4 FBLAN24
3E W3 FBLAP24
3E V4 FBLAN25
3E V3 FBLAP25
3E U10 FBLAN26
3E U9 FBLAP26
3E V9 FBLAN27
3E V8 FBLAP27
3E T9 FBHA_N23
3E T8 FBHA_P23
3E W10 FBHA_N20
3E W9 FBHA_P20
3E V11 FBHA_N21
3E U11 FBHA_P21
3E R7 FBHA_N22
3E R6 FBHA_P22
3A AU7 FBLAN0
3A AV7 FBLAP0
3A AT8 FB_LA_DEVCLK_N
3A AT7 FB_LA_DEVCLK_P
3A AT10 FBLAN2
3A AT9 FBLAP2
3A AV8 FBLAN3
3A AW8 FBLAP3
3A AU9 FBLAN4
3A AV9 FBLAP4
3A AW10 FB_LA_SYSREF_N
3A AW9 FB_LA_SYSREF_P
3A AP8 FBLAN6
3A AR8 FBLAP6
3A AU11 FBLAN7
3A AU10 FBLAP7
3A AN9 FBLAN8
3A AP9 FBLAP8
3A AP10 FBLAN9
3A AR10 FBLAP9
3A AR12 FBLAN10
3A AT12 FBLAP10
3A AP11 FBCLK0M2CN
3A AR11 FBCLK0M2CP
3A AL10 Refclk_3An
3A AM10 Refclk_3Ap
3A AK12 FBLAN11
3A AK11 FBLAP11
3A AL12 FBLAN12
3A AM12 FBLAP12
3A AM11 FBLAN13
3A AN11 FBLAP13
3A AL14 FBLAN14
3A AL13 FBLAP14
3A AN13 FBLAN15
3A AN12 FBLAP15
3A AJ15 FBLAN16
3A AK15 FBLAP16
3A AH13 FBLAN17
3A AH12 FBLAP17
3A AJ13 FBLAN18
3A AK13 FBLAP18
3A AF14 FBLAN19
3A AG14 FBLAP19
3A AH14 FMB_SYNC_AB
3A AJ14 FMB_SYNC_CD
3A AF15 FMB_SYNCN
3A AG15 FMB_SYNCP
Level Two Title