Arria® 10 SX SoC Development Kit User Guide

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ID 683227
Date 11/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 SX SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Development Kit Components 6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide A. Safety and Regulatory Compliance Information
1. Arria® 10 SX SoC Development Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC FPGA Embedded Development Suite (EDS) 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver 2.3.5. SD Card Image with Example Software
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Development Kit Components x
5.1. Board Overview 5.2. Featured Device: Arria® 10 SX SoC 5.3. MAX® V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over Onboard Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. Onboard Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe* 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughter Cards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Arria® 10 SX SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Development Kit Components
6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide
A. Safety and Regulatory Compliance Information

6. Document Revision History for the Arria® 10 SX SoC Development Kit User Guide

Document Version Changes
2025.11.27
  • Retitled document to Arria® 10 SX SoC Development Kit User Guide.
  • Updated mentions of " Arria® 10 SoC" to " Arria® 10 SX SoC".
  • Updated the Arria® 10 SX SoC Development Kit Overview chapter:
    • Updated and moved the block diagram from Arria® 10 SX SoC Development Kit Overview chapter to a new topic—Block Diagram.
    • Merged content from the General Description into the Arria® 10 SX SoC Development Kit Overview topic.
    • Retitled topic Board Component Blocks to Feature Summary.
    • Added a new topic—Box Contents.
  • Updated the Getting Started chapter:
    • Retitled topic Board Inspection to Before You Begin.
    • Added new topics:
      • Handling the DIP Switches
      • Software and Driver Installation
      • Installing the Quartus® Prime Pro Edition Software
    • Removed the following topics:
      • Installing the Subscription Edition of the Quartus® Prime Design Software
      • Activating Your License
    • Updated and retitled topic Development Kit Installer to Installing the Development Kit.
  • Retitled chapter Board Components to Develpoment Kit Components.
  • Removed the Additional Information appendix chapter.
  • Added new appendix chapter—Safety and Regulatory Compliance Information.
  • Restructured the document for clarity.
  • Made editorial edits throughout the document.
  • Rebranded to Altera.
2024.02.21
  • Rebranded the document to the correct product names and trademarks.
  • Text edits only; no new technical information.
2023.07.12
  • Retitled the document from Arria 10 SoC Development Kit User Guide to Arria® 10 SoC Development Kit User Guide.
  • Minor text edits.
Date Version Changes
August 2018 2018.08.09

Updated Memory. HPS-EMIF only supports DDR3 and DDR4 while the FPGA EMIF supports the rest of the protocols.
September 2017 2017.09.05
August 2017 2017.08.08 Added a Caution note to Handling the Board
December 2016 2016.12.29
  • Updated FMCA LVDS Signal I/O Assignments Table in FMC
December 2016 2016.12.22 Updates:
July 2016 2016.07.29 Updated:
June 2016 2016.06.30 Added: Updated:
May 2016 2016.05.26 Updated:
May 2016 2016.05.24 Updated: FPGA-I/O MAX V Interface
April 2016 2016.04.04 Updated:
March 2016 2016.03.18 Production release.
Level Two Title