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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP
The Debug Endpoint Avalon® interface is a JTAG Avalon memory-mapped interface that provides access to the reconfiguration register space of the GTS PMA through System Console. The Quartus® Prime software inserts the debug interconnect fabric to connect the GTS PMA with JTAG.
To enable the Debug Endpoint Avalon® Interface, follow these steps:
- In the Avalon® Memory-Mapped Interface tab of the GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor, enable the following options:
- Enable Avalon® Memory Mapped interface
- Enable Direct PHY soft CSR
- Enable Debug Endpoint on Avalon® interface
Note: You must enable the Enable readdatavalid port on Avalon interface option in the current Quartus® Prime Pro Edition software release in order to perform a read operation. This issue is planned to be fixed in a future release.Figure 58. Avalon® Memory-Mapped Interface Parameter Settings to Enable Debug Endpoint - Connect the clock and reset signals to the i_reconfig_clk and i_reconfig_reset ports of the reconfiguration interface.
- Connect the other reconfiguration interface signals:
- i_reconfig_write
- i_reconfig_read
- i_reconfig_address
- i_reconfig_writedata
- i_reconfig_byteenable
Note: If you do not connect the reconfiguration interface signals appropriately, the debug endpoint functions unexpectedly.