GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP

The Debug Endpoint Avalon® interface is a JTAG Avalon memory-mapped interface that provides access to the reconfiguration register space of the GTS PMA through System Console. The Quartus® Prime software inserts the debug interconnect fabric to connect the GTS PMA with JTAG.
To enable the Debug Endpoint Avalon® Interface, follow these steps:
  1. In the Avalon® Memory-Mapped Interface tab of the GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor, enable the following options:
    • Enable Avalon® Memory Mapped interface
    • Enable Direct PHY soft CSR
    • Enable Debug Endpoint on Avalon® interface
    Note: You must enable the Enable readdatavalid port on Avalon interface option in the current Quartus® Prime Pro Edition software release in order to perform a read operation. This issue is planned to be fixed in a future release.
    Figure 58.  Avalon® Memory-Mapped Interface Parameter Settings to Enable Debug Endpoint
  2. Connect the clock and reset signals to the i_reconfig_clk and i_reconfig_reset ports of the reconfiguration interface.
  3. Connect the other reconfiguration interface signals:
    • i_reconfig_write
    • i_reconfig_read
    • i_reconfig_address
    • i_reconfig_writedata
    • i_reconfig_byteenable
    to ground, assuming no FPGA core logic controls the reconfiguration interface.
    Note: If you do not connect the reconfiguration interface signals appropriately, the debug endpoint functions unexpectedly.