GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing

This section details the steps you should follow to configure the GTS PMA/FEC Direct PHY Intel FPGA IP in order to bring-up the GTS PMA for hardware testing using System Console in the Quartus® Prime software. You can use these methods to configure the GTS PMA analog settings to enable functions such as serial loopback, PRBS generators and checkers, to modify TX equalizer settings, and BER measurements.

You can choose either of the following methods to access the PMA registers via JTAG using System Console: