GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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5.5. GTS Reset Sequencer Intel FPGA IP Design Flow

The design flow for the GTS Reset Sequencer Intel FPGA IP is described below:
  1. Add the GTS Reset Sequencer Intel FPGA IP from the IP Catalog into your design as shown in the following figure.
    Figure 70. IP Catalog
  2. Select the total Number of Bank(s) that you want to use for the GTS Reset Sequencer Intel FPGA IP as shown in the following figure.
    Figure 71. IP Parameters for Bank Selection
  3. Select the total Number of Reset Sequencer Lane(s) that you want to use for the GTS Reset Sequencer Intel FPGA IP as shown in the following figure.
    Figure 72. IP Parameters for Lane Selection
  4. Connect o_src_rs_grant and i_src_rs_req to the channels. The o_src_rs_grant and i_src_rs_req must be connected to the same channel so that the reset operation works accordingly. For simplex applications, each simplex PMA occupies one channel; therefore, it needs its own o_src_rs_grant and i_src_rs_req signals.
    Note: The dual-simplex mode is planned to be supported in a future Quartus® Prime Pro Edition software release.
  5. Connect o_pma_cu_clk to i_pma_cu_clk input of the GTS PMA/FEC Direct PHY Intel FPGA IP and protocol IPs. If there are two or more IPs in the same bank, the IPs must be connected to the same o_pma_cu_clk. For any separate bank, make sure to use different o_pma_cu_clk for each bank.
  6. For channels that need to be prioritized for reset sequencing, tie i_src_rs_priority to 1 for that specific channel based on the connection of bits o_src_rs_grant and i_src_rs_req for that channel. For non-priority (normal) reset sequence channels, tie the i_src_rs_priority to 0. For example, the value 4’b0010, sets the priority to lane 2.
Note: You can skip steps 3. 4, and 6. if you set the Enable PCIE and/or HPS USB3.1 only design option to Enable in the IP parameter GUI. If you are using Platform Designer, for steps 4 and 5, you must connect o_src_rs_grant, i_src_rs_req, and o_pma_cu_clk signals using wire-level expressions. Refer Editing Wire-Level Expressions in the Quartus® Prime Pro Edition User Guide: Platform Designer for more details.