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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
The design flow for the GTS Reset Sequencer Intel FPGA IP is described below:
- Add the GTS Reset Sequencer Intel FPGA IP from the IP Catalog into your design as shown in the following figure.
Figure 70. IP Catalog
- Select the total Number of Bank(s) that you want to use for the GTS Reset Sequencer Intel FPGA IP as shown in the following figure.
Figure 71. IP Parameters for Bank Selection
- Select the total Number of Reset Sequencer Lane(s) that you want to use for the GTS Reset Sequencer Intel FPGA IP as shown in the following figure.
Figure 72. IP Parameters for Lane Selection
- Connect o_src_rs_grant and i_src_rs_req to the channels. The o_src_rs_grant and i_src_rs_req must be connected to the same channel so that the reset operation works accordingly. For simplex applications, each simplex PMA occupies one channel; therefore, it needs its own o_src_rs_grant and i_src_rs_req signals.
Note: The dual-simplex mode is planned to be supported in a future Quartus® Prime Pro Edition software release.
- Connect o_pma_cu_clk to i_pma_cu_clk input of the GTS PMA/FEC Direct PHY Intel FPGA IP and protocol IPs. If there are two or more IPs in the same bank, the IPs must be connected to the same o_pma_cu_clk. For any separate bank, make sure to use different o_pma_cu_clk for each bank.
- For channels that need to be prioritized for reset sequencing, tie i_src_rs_priority to 1 for that specific channel based on the connection of bits o_src_rs_grant and i_src_rs_req for that channel. For non-priority (normal) reset sequence channels, tie the i_src_rs_priority to 0. For example, the value 4’b0010, sets the priority to lane 2.
Note: You can skip steps 3. 4, and 6. if you set the Enable PCIE and/or HPS USB3.1 only design option to Enable in the IP parameter GUI. If you are using Platform Designer, for steps 4 and 5, you must connect o_src_rs_grant, i_src_rs_req, and o_pma_cu_clk signals using wire-level expressions. Refer Editing Wire-Level Expressions in the Quartus® Prime Pro Edition User Guide: Platform Designer for more details.