GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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4.5.1. Example flow to indicate System PLL reference clock is ready

Here are the steps to indicate that the system PLL reference clock is ready.

If reference clock is ready before device configuration:
  1. Tie i_refclk_ready pin to high.
If reference clock is not ready before device configuration:
  1. Wait until the system PLL's reference clock is available and stable.
  2. Set i_refclk_ready pin to high.
Note: For PCIe* you must select one of the PCIe* modes in the GTS System PLL Clocks Intel FPGA IP. When you select PCIe* mode, the i_refclk_ready port is not available. You must make sure that the reference clock to the system PLL is available and stable before device configuration.