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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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4.1. IP Parameters
The table below lists the IP parameters for the GTS System PLL Clocks Intel FPGA IP.
Figure 66. GTS System PLL Clock Intel FPGA IP Parameter Editor
Parameter | Values | Description |
---|---|---|
System PLL | ||
Use case of system PLL | TRANSCEIVER_USE_CASE | Use case of system PLL. Use the TRANSCEIVER_USE_CASE to supply clock to the transceivers. |
Mode of system PLL | User Configuration | Selects the mode of system PLL. Only available when Use case of system PLL is set to TRANSCEIVER_USE_CASE.
Note: The frequency number in the preset labels are abbreviated; they are not the full precise frequencies. Refer to the Preset Reference Clock and Output Frequencies table for the full frequencies.
The default value is ETHERNET_FREQ_322_156. |
User PCIe* -based Configuration | ||
ETHERNET_FREQ_322_156 | ||
ETHERNET_FREQ_322_322 | ||
PCIE_FREQ_250 | ||
PCIE_FREQ_275 | ||
PCIE_FREQ_300 | ||
PCIE_FREQ_325 | ||
PCIE_FREQ_350 | ||
PCIE_FREQ_375 | ||
PCIE_FREQ_400 | ||
PCIE_FREQ_425 | ||
PCIE_FREQ_450 | ||
PCIE_FREQ_475 | ||
Refclk frequency | 25.78125 MHz to 380 MHz | Specifies the reference clock frequency. |
Output frequency C0 | 31.25 MHz to 1000 MHz | Specifies the output frequency of the system PLL C0 in MHz. In the background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points.
Note: You must ensure that the output frequency of the system PLL and the GTS PMA/FEC Direct PHY Intel FPGA IP are set to the same frequency if you are using the system PLL clocking mode.
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