GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design

To generate the example design you need to open the GTS PMA/FEC Direct PHY Intel FPGA IP and go to the Example Design tab. The GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor includes the Generate Example Design function to easily create and generate simulation files to simulate a GTS PMA or FEC direct mode example design.

You can currently select one out of the seven Example Design Options for generation as shown in the following table.
Table 66.  Example Design Options
Example Design Options Description
1 x 10.3125G FEC Direct Mode (System PLL Clocking) One NRZ Firecode FEC Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode
1 x 10.3125G RSFEC Direct Mode (System PLL Clocking) One NRZ RS-FEC FEC Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode
1 x 17.16G RSFEC Direct Mode (System PLL Clocking) One NRZ RS-FEC FEC Direct GTS lane, with a throughput of 17.610 Gbps, with System PLL clocking mode
1 x 10.3125G PMA Direct Mode (System PLL Clocking) with Custom Cadence

One NRZ PMA Direct GTS lane, with a throughput of 10.3125 Gbps, with System PLL clocking mode and custom cadencing

4 x 10.3125G PMA Direct Mode (PMA Clocking)

Four NRZ PMA Direct GTS lane, with 10.3125 Gbps per PMA lane, with PMA clocking mode

1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence

One NRZ PMA Direct GTS lane, with a throughput of 1Gbps, with System PLL clocking mode and custom cadencing

1x 3.125G PMA Direct Mode (System PLL Clocking) with Custom Cadence

One NRZ PMA Direct GTS lane, with a throughput of 3.125 Gbps, with System PLL clocking mode and custom cadencing.

To generate an example design, follow the steps below:
  1. Go to the Example Design tab in the GTS PMA/FEC Direct PHY Intel FPGA IP.
  2. Select one of the example designs from the drop-down menu. If you select None you cannot generate the example design.
  3. Click the Acknowledgment option box. This option is to remind you that only the example design you specify in the drop-down menu is generated. If you make any modification to the parameter settings of the IP after selecting the Example Design options from the drop down list, the changes you make to the IP parameters do not take effect. Only the parameters defined for the Example Design options in Example Design Options table take effect. If you do not check the acknowledgment box, you cannot generate the example design.
  4. Ensure steps 2. and step 3. are done, then click Generate Example Design. Clicking Generate Example Design completes the IP Generation. An example design folder is generated containing the Quartus® Prime project (.qpf), settings (.qsf), and IP files. In addition, there are two folders created named rtl and testbench containing the RTL and simulation testbench files in the following location:
    <Project Folder>/<directphy_example_design/example_design>
Figure 76. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Steps
Note: If you select any of the seven available Example Design Options, but change the GTS PMA/FEC Direct PHY Intel FPGA IP settings in the GUI thereafter, the example design generated does not follow the changed settings for the GTS PMA/FEC Direct PHY Intel FPGA IP. The example design generation only takes the Example Design Options listed in Example Design tab of the IP Parameter editor. Any other changes that you make to the GTS PMA/FEC Direct PHY Intel FPGA IP settings are not applied during example design generation.