GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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Document Table of Contents

3.3.2. Common Datapath Options

Figure 39. GTS PMA/FEC Direct PHY Intel FPGA IP Parameter Editor
Table 17.  Common Datapath Options Parameters
Parameter Values Description
PMA configuration rules Basic,

DISPLAY PORT 25,

OTN,

SDI,

CPRI,

HDMI,

Selects the protocol configuration rules for the GTS PMA. This parameter governs the rules for correct settings of individual parameters within the PMA.

Certain features of the PMA are available only for specific protocol configuration rules. This parameter is not a preset. You must still correctly set all other parameters for your specific protocol and application needs.

Default value is Basic.

Number of PMA Lanes For TX Simplex and Duplex : 1, 2, 4, 6, 8

For RX Simplex : 1, 2, 3, 4, 6, 8

Specifies the total number of PMA lanes in a bonded group. For example, if the value is 4, this means there are 4 PMA lanes bonded in the same group and share the same bonding clock. A value of 1 means there is no bonding. The number of PMA lanes is 1 when FEC is enabled.

Default value is 1.

Datapath clocking mode

PMA

System PLL

Specifies whether the PMA parallel clock or System PLL is used to clock the TX/RX datapath.

Required to use System PLL when Enable FEC is on. Default value is System PLL.

System PLL Frequency 32.5 to 1000 MHz
Specifies the system PLL clock frequency (MHz) and applicable if datapath clocking mode is selected as system PLL. Default value is 322.265625 MHz.
Note: You must ensure that the system PLL frequency and GTS System PLL Clocks Intel FPGA IP frequency is set to the same value if you are using the system PLL clocking mode.
PMA mode Duplex, TX Simplex and RX Simplex

Specifies the PMA operation mode. TX simplex and RX simplex can operate at independent rates at different PMA lanes. Default value is Duplex.

PMA Data Rate

E-Series (Device Group B):

10312.5 Mbps (default)

17160 Mbps (maximum)

Specifies the PMA data rate in units of Mbps (Mb/sec). Default value for:

E-series (Device Group B): 10312.5 Mbps

PMA Parallel Clock Frequency Data rate/PMA width Displays PMA parallel clock frequency which is PMA data rate divided by PMA interface width in MHz. Default value is Data rate / PMA Width.
PMA Width 8, 10, 16, 20, 32

Specifies the PMA data width. Supported Data width is 8, 10, 16, 20 and 32 bit. Default value is 32

Provide separate interface for each PMA
Note: This feature is preliminarily and is planned to be fully supported in a future Quartus® Prime Pro Edition software release.
On/Off
When enabled, the GTS PMA/FEC Direct PHY Intel FPGA IP presents separate data and clock interfaces for each PMA lane, rather than a wide bus. Default value is Off.
Note: When the Enable FEC option is on, a separate interface is not available for each PMA by use of the Provide separate interface for each PMA option.
Enable refclock to core On/Off Enable the reference clock to FPGA core feature.
Table 18.  TX/RX Common PMA Options Parameters
Parameter Values Description
Loopback mode

disabled

parallel

Selects the PMA loopback mode. Default value is disabled.
Note:

For the parallel loopback mode, when you do not have RX input serial data coming into the receiver, you need to override the soft reset controller (SRC) by setting the soft CSR register 0x10018[0]. In order for the TX to RX parallel loopback mode to function, you need to set this bit to 1'b1 to override the SRC from monitoring the PMA block status. Once you are out of TX to RX parallel loopback mode, you can set this bit back to 1'b0.

You do not have to control this bit if you have RX serial data coming into the receiver. Refer to the GTS PMA/FEC Direct PHY IP Register Map for more information.

25 Display Port is supported only in duplex mode in the current Quartus® Prime Pro Edition software release.