Visible to Intel only — GUID: xrn1681414813661
Ixiasoft
Visible to Intel only — GUID: xrn1681414813661
Ixiasoft
3.1. IP Overview
The GTS PMA/FEC Direct PHY Intel FPGA IP is for use in proprietary protocol configurations. The GTS PMA/FEC Direct PHY Intel FPGA IP enables access to the PMA Direct and FEC Direct modes.
The PMA Direct mode bypasses the MAC and FEC Hard IP blocks. You can configure the PMA interface and core interface FIFOs in the datapath into various modes, including elastic and phase compensation modes.
The FEC Direct mode bypasses the MAC and PCS Hard IP blocks. In this mode, the PMA interface and core interface FIFOs in the datapath are set to elastic and phase compensation modes, respectively.
You can use the PMA/FEC Direct PHY Intel FPGA IP to configure the datapath into the PMA and FEC direct modes. If you enable the FEC mode, the FEC block is enabled. The top-level file that generates with the IP instance includes all the available ports for your configuration. Use these ports to connect the GTS PMA/FEC Direct PHY Intel FPGA IP to other IP cores in your design, such as GTS System PLL Clock Intel FPGA IP, GTS Reset Sequencer Intel FPGA IP, TX and RX serial data pins, data generator and data checker soft IP.