GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies

Table 59.  Preset Reference Clock and Output Frequencies
Mode of System PLL - System PLL Reference Clock (MHz) Output Frequency (MHz)
PCIE_FREQ_250 100 250
PCIE_FREQ_275 100 275
PCIE_FREQ_300 100 300
PCIE_FREQ_325 100 325
PCIE_FREQ_350 100 350
PCIE_FREQ_375 100 375
PCIE_FREQ_400 100 400
PCIE_FREQ_425 100 425
PCIE_FREQ_450 100 450
PCIE_FREQ_475 100 475
ETHERNET_FREQ_322_156 156.25 322.265625
ETHERNET_FREQ_322_322 322.265625 322.265625
Table 60.  Port Connection Guidelines between GTS System PLL Clock Intel FPGA IP and GTS PMA/FEC Direct PHY Intel FPGA IP
GTS System PLL Clock Intel FPGA IP GTS PMA/FEC Direct PHY Intel FPGA IP
System PLL
o_syspll_c0 i_system_pll_clk
o_pll_lock i_system_pll_lock