GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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Document Table of Contents

3.3.6. Avalon® Memory-Mapped Interface Options

Figure 45.  Avalon® Memory-Mapped Interface Tab in Parameter Editor
Table 24.   Avalon® Memory-Mapped Interface Parameters
Parameter Values Description
Enable Avalon® Memory Mapped Interface On/Off

Enables or disables the Avalon® memory mapped interface. Default value is Off.

Enable Direct PHY soft CSR On/Off

Enables or disables the soft CSR feature. Default value is Off.

Enable readdatavalid port on Avalon® interface
Note: You must enable this port in the current Quartus® Prime Pro Edition software release in order to perform a read operation. This issue is planned to be fixed in a future release.
On/Off

Off specifies no o_reconfig_readdatavalid port and o_reconfig_waitrequest low indicates data valid.

On specifies o_reconfig_readdatavalid port is enabled and indicates data valid. Default value is Off.

Enable separate Avalon® interface per PMA
Note: This feature is preliminarily and is planned to be fully supported in a future Quartus® Prime Pro Edition software release.
On/Off

Off specifies shared Avalon® interface.

On specifies split interface, if multiple interfaces available with selected targets. Default value is Off.

Enable Debug Endpoint on Avalon® interface On/Off When On, the GTS PMA/FEC Direct PHY Intel FPGA IP includes an embedded Debug Endpoint that internally connects Avalon® memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the FEC and the PMA interface block. The IP can perform certain tests and debug functions through JTAG using the System Console. This option may require that you include a jtag_debug link in the system. Default value is Off.