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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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6.4.1. Modifying the Example Design and Performing Simulation
If you want to modify the example design to change the data rate, system PLL clock frequency, increase the number of PMA lanes and so on, you can reuse the existing example design and perform following changes:
- Update and re-configure the GTS PMA/FEC Direct PHY Intel FPGA IP, GTS System PLL Clock Intel FPGA IP, and GTS Reset Sequencer Intel FPGA IP.
- Generate and instantiate the GTS Reset Sequencer Intel FPGA IP and make sure the connections of the i_src_rs_req and o_src_rs_grant ports are connected correctly to the GTS PMA/FEC Direct PHY Intel FPGA IP. If you add more GTS transceiver banks in the design, you must ensure proper connections for the o_pma_cu_clk port. Refer to Implementing the GTS Reset Sequencer Intel FPGA IP for more information.
Note: You must ensure that the system PLL frequency in the GTS PMA/FEC Direct PHY Intel FPGA IP and GTS System PLL Clocks Intel FPGA IP is set to the same value, if you are using the system PLL clocking mode. - Regenerate the IPs by clicking Generate HDL.
- Run Analysis and Synthesis.
- Initialize and make changes to the testbench variable files in the following example design directory <example_design/rtl>:
- testwrap_pma_direct.sv and test_tst.sv
- param_defines.iv and param_defines1.iv
- After making the necessary changes, refer to Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench to run the simulation and analyze results.
Note: For a successful simulation, you must ensure that the Refclk frequency of the GTS System PLL Clocks Intel FPGA IP and RX CDR reference clock frequency together with TX PLL Integer mode reference clock frequency in the GTS PMA/FEC Direct PHY Intel FPGA IP are driven from the same clock source.