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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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2.4. Forward Error Correction (FEC) Architecture
The FEC block is located between the PCS and PMA interface. Each FEC core can be used to implement multiple FEC modes as shown in the following table..
FEC Mode | Specification | FEC Compliance Specification | Example Protocols |
---|---|---|---|
Firecode15 | IEEE | IEEE 802.3 BASE-R Firecode (CL 74) | 10GbE, 25GbE-1 |
RS-FEC | IEEE | IEEE 802.3 RS(528, 514) (CL 91) | 25GbE-1 |
IEEE | IEEE 802.3 RS(528, 514) (CL 91) ETC | 25GbE-1 | |
Fibre Channel | Fibre Channel RS(528, 514) | Fibre Channel 16G, CPRI 10.1376 and 24.3302 Gbps | |
ITU-T 709.4 | OTU25u RS(528, 514) | OTU25 |
Note: You can use the FEC mode for the entire range of line rates from 1 Gbps to the transceiver maximum supported data rate for custom applications. If your configuration has multiple interfaces in one FEC block, the block must be clocked by the same system PLL and requires custom cadence. Refer to Datapath Clock Cadences for details.
15 Firecode FEC 25GbE mode is supported in D-Series and E-Series Device Group A. Firecode FEC 25GbE mode is not supported in E-Series Device Group B.