GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4. Forward Error Correction (FEC) Architecture

The FEC block is located between the PCS and PMA interface. Each FEC core can be used to implement multiple FEC modes as shown in the following table..
Table 9.  Supported FEC Modes and Compliance Specifications
FEC Mode Specification FEC Compliance Specification Example Protocols
Firecode15 IEEE IEEE 802.3 BASE-R Firecode (CL 74) 10GbE, 25GbE-1
RS-FEC IEEE IEEE 802.3 RS(528, 514) (CL 91) 25GbE-1
IEEE IEEE 802.3 RS(528, 514) (CL 91) ETC 25GbE-1
Fibre Channel Fibre Channel RS(528, 514) Fibre Channel 16G, CPRI 10.1376 and 24.3302 Gbps
ITU-T 709.4 OTU25u RS(528, 514) OTU25
Note: You can use the FEC mode for the entire range of line rates from 1 Gbps to the transceiver maximum supported data rate for custom applications. If your configuration has multiple interfaces in one FEC block, the block must be clocked by the same system PLL and requires custom cadence. Refer to Datapath Clock Cadences for details.
15 Firecode FEC 25GbE mode is supported in D-Series and E-Series Device Group A. Firecode FEC 25GbE mode is not supported in E-Series Device Group B.