GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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Document Table of Contents

3.3.4.1. RX PMA Interface Parameters

Figure 43. RX PMA Interface Options in Parameter Editor
Table 22.   RX PMA Interface Parameters
Parameter Values Description
RX PMA Interface Parameters
RX PMA interface FIFO mode

Register

Elastic

Selects the RX PMA Interface FIFO mode. Default value is Elastic. Refer to PMA Direct Mode Support for more information,
Enable rx_pmaif_fifo_empty port On/Off Enables the port that indicates the RX PMA Interface FIFO's empty condition. Default value is Off.
Enable rx_pmaif_fifo_pempty port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially empty condition. Default value is Off.
Enable rx_pmaif_fifo_pfull port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially full condition. Default value is Off.
RX Core Interface Parameters
RX core interface FIFO mode

Phase compensation

Elastic 0

Specifies the mode for the RX Core Interface FIFO. Default value is Phase compensation.
Enable RX double width transfer On/Off Enables double width RX data transfer mode. In this mode, core logic can be clocked with a half rate clock. Default value is On.
Enable rx_fifo_full port On/Off Enables the optional o_rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with o_rx_clkout. Default value is Off.
Enable rx_fifo_empty port On/Off Enables the optional o_rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with o_rx_clkout. Default value is Off.
Enable rx_fifo_pfull port On/Off Enables the optional o_rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable rx_fifo_pempty port On/Off Enables the optional o_rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold. Default value is Off.
Enable rx_fifo_rd_en port On/Off Enables the optional i_rx_fifo_rd_en control input port. This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO. You must enable this read enable when using Elastic FIFO. Default value is Off.
RX Clock Options
Selected rx_clkout clock source

Word Clock

RX User Clock

Sys PLL Clock

Specifies the o_rx_clkout output port source. Default value is Sys PLL Clock.
Frequency of rx_clkout Output Displays the frequency of o_rx_clkout in MHz based on o_rx_clkout source selection.
Enable rx_clkout2 port On/Off Enables the optional o_rx_clkout2 output clock. Default value is Off.
Selected rx_clkout2 clock source

Word Clock

RX User Clock

Sys PLL Clock

Specifies the o_rx_clkout output port source. Default value is Word Clock.
rx_clkout2 clock div by 1, 2, 4 Selects the RX clock out 2 divider setting that divides out the o_rx_clkout2 output port source. Default value is 1.
Frequency of rx_clkout2 Output Displays the frequency of o_rx_clkout2 in MHz based on o_rx_clkout2 source selection and o_rx_clkout2 clock divide by factor.
RX User Clock Settings
RX user clock div by 12-139.5 Division factor from Fvco of RX CDR to RX user clock. Values from 12 to 139.5 are acceptable in 0.5 increments. Default value is 100.
RX user clock Frequency Output Displays the frequency of RX user clock in MHz based on RX user clock divide by factor.