GTS Transceiver PHY User Guide

ID 817660
Date 4/01/2024
Public

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Document Table of Contents

3.3.3.1. TX PMA Interface Parameters

Figure 41. TX PMA Interface Parameters in Parameter Editor
Table 20.  TX PMA Interface Parameters
Parameter Values Description
TX PMA Interface Parameters
TX PMA interface FIFO mode

Register

Elastic

Selects the TX PMA Interface FIFO mode. Default value is Elastic. Refer to PMA Direct Mode Support for more information,
Enable tx_pmaif_fifo_empty port On/Off Enables the port that indicates the TX PMA Interface FIFO's empty condition. Default value is Off.
Enable tx_pmaif_fifo_pempty port On/Off Enables the port that indicates the TX PMA Interface FIFO's partially empty condition. Default value is Off.
Enable tx_pmaif_fifo_pfull port On/Off Enables the port that indicates the TX PMA Interface FIFO's partially full condition. Default value is Off.
TX Core Interface Parameters
Enable custom cadence generation ports and logic On/Off Enables optional custom cadence generation (CCG) logic and ports (o_tx_cadence, i_tx_cadence_fast_clk, i_tx_cadence_slow_clk). CCG logic can be enabled when Datapath clocking mode is set to System PLL. Default value is Off. Refer to Custom Cadence Generation Ports and Logic for more information.
Enable tx_cadence_slow_clk_locked port On/Off

If i_tx_cadence_slow_clk is not directly coming from TX PLL (word clock/TX user clock), but rather comes from another clock source, you must turn on this option in the parameter editor. i_tx_cadence_slow_clk_locked port must be driven by the PLL locked output of the other PLL source used for slow clock. Default value is Off.

TX core interface FIFO mode

Phase Compensation

Elastic 26

Specifies the mode for the TX Core Interface FIFO. Default value is Phase Compensation. Elastic mode is only supported for PMA Clocking mode.
Enable TX double width transfer

On/Off

Enables double width TX data transfer mode. In this mode, the core logic can be clocked with half rate clock. Default value is Off.
Enable tx_fifo_full port On/Off Enables the optional o_tx_fifo_full status output port. This signal indicates when the TX core FIFO has reached the full threshold. This signal is synchronous with o_tx_clkout. Default value is Off.
Enable tx_fifo_empty port On/Off Enables the optional o_tx_fifo_empty status output port. This signal indicates when the TX core FIFO has reached the empty threshold. This signal is synchronous with o_tx_clkout. Default value is Off.
Enable tx_fifo_pfull port On/Off Enables the optional o_tx_fifo_pfull status output port. This signal indicates when the TX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable tx_fifo_pempty port On/Off Enables the optional o_tx_fifo_pempty status output port. This signal indicates when the TX core FIFO has reached the specified partially empty threshold. Default value is Off.
TX Clock Options
Selected tx_clkout clock source

Word Clock

TX User Clock

Sys PLL Clock

Specifies the o_tx_clkout output port source. Default value is Sys PLL Clock.
tx_clkout clock div by 1, 2, 4 Selects the TX clock output divider setting that divides out the o_tx_clkout output port source. Default value is 1.
Frequency of tx_clkout Output Displays the frequency of o_tx_clkout in MHz based on o_tx_clkout source selection.
Enable tx_clkout2 port On/Off Enables the optional o_tx_clkout2 output clock. Default value is Off.
Selected tx_clkout2 clock source

Word Clock

TX User Clock

Sys PLL Clock

Specifies the o_tx_clkout2 output port source. Default value is Word Clock.
tx_clkout2 clock div by 1, 2, 4 Selects the TX clock out 2 divider setting that divides out the o_tx_clkout2 output port source. Default value is 1.
Frequency of tx_clkout2 Output Displays the frequency of o_tx_clkout2 in MHz based on o_tx_clkout2 source selection and o_tx_clkout2 clock divide by factor.
TX User Clock Settings
TX user clock div by 12 to 139.5 Division factor from the Fvco of the TX PLL VCO to TX user clock. Values from 12 to 139.5 are acceptable in 0.5 increments. Default value is 100.
TX user clock frequency Output Displays the frequency of the TX user clock in MHz based on the TX user clock divide by factor.
26 Elastic mode for TX/RX Core Interface FIFO is planned to be supported in a future release.